X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fwinsys%2Famdgpu%2Fradv_amdgpu_cs.c;h=939c221e0c8c0b5c3587896c214f7607fa6a4810;hb=a639d40f1330351924d736ca260de764734f9ef7;hp=adb855f97de9afe37d2b5aa763d4a6fcfd6d388b;hpb=43eb761cad8a7941788735d2d7a5f10a36a25148;p=mesa.git diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index adb855f97de..939c221e0c8 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -202,7 +202,8 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws, if (cs->ws->use_ib_bos) { cs->ib_buffer = ws->buffer_create(ws, ib_size, 0, RADEON_DOMAIN_GTT, - RADEON_FLAG_CPU_ACCESS); + RADEON_FLAG_CPU_ACCESS| + RADEON_FLAG_NO_INTERPROCESS_SHARING); if (!cs->ib_buffer) { free(cs); return NULL; @@ -215,7 +216,7 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws, return NULL; } - cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->va; + cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va; cs->base.buf = (uint32_t *)cs->ib_mapped; cs->base.max_dw = ib_size / 4 - 4; cs->ib_size_ptr = &cs->ib.size; @@ -287,7 +288,8 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size) cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0, RADEON_DOMAIN_GTT, - RADEON_FLAG_CPU_ACCESS); + RADEON_FLAG_CPU_ACCESS| + RADEON_FLAG_NO_INTERPROCESS_SHARING); if (!cs->ib_buffer) { cs->base.cdw = 0; @@ -306,8 +308,8 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size) cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer, 8); cs->base.buf[cs->base.cdw++] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0); - cs->base.buf[cs->base.cdw++] = radv_amdgpu_winsys_bo(cs->ib_buffer)->va; - cs->base.buf[cs->base.cdw++] = radv_amdgpu_winsys_bo(cs->ib_buffer)->va >> 32; + cs->base.buf[cs->base.cdw++] = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va; + cs->base.buf[cs->base.cdw++] = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32; cs->ib_size_ptr = cs->base.buf + cs->base.cdw; cs->base.buf[cs->base.cdw++] = S_3F2_CHAIN(1) | S_3F2_VALID(1); @@ -360,7 +362,7 @@ static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs) cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]); cs->num_old_ib_buffers = 0; - cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->va; + cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va; cs->ib_size_ptr = &cs->ib.size; cs->ib.size = 0; } @@ -471,6 +473,9 @@ static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs, return; } + if (bo->is_local) + return; + radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority); } @@ -541,6 +546,10 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws, } else if (count == 1 && !extra_bo && !extra_cs && !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) { struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0]; + if (cs->num_buffers == 0) { + *bo_list = 0; + return 0; + } r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles, cs->priorities, bo_list); } else { @@ -556,7 +565,10 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws, if (extra_cs) { total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers; } - + if (total_buffer_count == 0) { + *bo_list = 0; + return 0; + } amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count); uint8_t *priorities = malloc(sizeof(uint8_t) * total_buffer_count); if (!handles || !priorities) { @@ -721,7 +733,8 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx, "see dmesg for more information.\n"); } - amdgpu_bo_list_destroy(bo_list); + if (bo_list) + amdgpu_bo_list_destroy(bo_list); if (fence) radv_amdgpu_request_to_fence(ctx, fence, &request); @@ -795,7 +808,8 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx, "see dmesg for more information.\n"); } - amdgpu_bo_list_destroy(bo_list); + if (bo_list) + amdgpu_bo_list_destroy(bo_list); if (r) return r; @@ -856,7 +870,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, } assert(cnt); - bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS); + bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING); ptr = ws->buffer_map(bo); if (preamble_cs) { @@ -886,7 +900,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, } ib.size = size; - ib.ib_mc_address = ws->buffer_get_va(bo); + ib.ib_mc_address = radv_buffer_get_va(bo); request.ip_type = cs0->hw_ip; request.ring = queue_idx; @@ -905,7 +919,8 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, "see dmesg for more information.\n"); } - amdgpu_bo_list_destroy(bo_list); + if (bo_list) + amdgpu_bo_list_destroy(bo_list); ws->buffer_destroy(bo); if (r) @@ -951,7 +966,6 @@ static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, return ret; } - static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr) { struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs; @@ -964,19 +978,19 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr) bo = (struct radv_amdgpu_winsys_bo*) (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]); - if (addr >= bo->va && addr - bo->va < bo->size) { + if (addr >= bo->base.va && addr - bo->base.va < bo->size) { if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) - return (char *)ret + (addr - bo->va); + return (char *)ret + (addr - bo->base.va); } } if(cs->ws->debug_all_bos) { pthread_mutex_lock(&cs->ws->global_bo_list_lock); list_for_each_entry(struct radv_amdgpu_winsys_bo, bo, &cs->ws->global_bo_list, global_list_item) { - if (addr >= bo->va && addr - bo->va < bo->size) { + if (addr >= bo->base.va && addr - bo->base.va < bo->size) { if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) { pthread_mutex_unlock(&cs->ws->global_bo_list_lock); - return (char *)ret + (addr - bo->va); + return (char *)ret + (addr - bo->base.va); } } } @@ -987,7 +1001,7 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr) static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs, FILE* file, - uint32_t trace_id) + const int *trace_ids, int trace_id_count) { struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs; void *ib = cs->base.buf; @@ -998,21 +1012,40 @@ static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs, num_dw = cs->ib.size; } assert(ib); - ac_parse_ib(file, ib, num_dw, trace_id, "main IB", cs->ws->info.chip_class, - radv_amdgpu_winsys_get_cpu_addr, cs); + ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB", + cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs); } -static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_ws) +static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority) +{ + switch (radv_priority) { + case RADEON_CTX_PRIORITY_REALTIME: + return AMDGPU_CTX_PRIORITY_VERY_HIGH; + case RADEON_CTX_PRIORITY_HIGH: + return AMDGPU_CTX_PRIORITY_HIGH; + case RADEON_CTX_PRIORITY_MEDIUM: + return AMDGPU_CTX_PRIORITY_NORMAL; + case RADEON_CTX_PRIORITY_LOW: + return AMDGPU_CTX_PRIORITY_LOW; + default: + unreachable("Invalid context priority"); + } +} + +static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_ws, + enum radeon_ctx_priority priority) { struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws); struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx); + uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority); int r; if (!ctx) return NULL; - r = amdgpu_cs_ctx_create(ws->dev, &ctx->ctx); + + r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx); if (r) { - fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create failed. (%i)\n", r); + fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r); goto error_create; } ctx->ws = ws; @@ -1020,7 +1053,8 @@ static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_w assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096); ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8, RADEON_DOMAIN_GTT, - RADEON_FLAG_CPU_ACCESS); + RADEON_FLAG_CPU_ACCESS| + RADEON_FLAG_NO_INTERPROCESS_SHARING); if (ctx->fence_bo) ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo); if (ctx->fence_map)