X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2FSConscript;h=10ed03c3d5ceff8a788eb53e6d25b496a98e2fec;hb=9d4a1bf2ba936499277b96054fbc83c478c0c6be;hp=ff460dafd5e67dcff854a9463d0ce4dc74d4156d;hpb=6ee38f143ec8796b819a1db901828a4903607c19;p=gem5.git

diff --git a/src/arch/SConscript b/src/arch/SConscript
index ff460dafd..10ed03c3d 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -28,13 +28,9 @@
 #
 # Authors: Steve Reinhardt
 
-import os.path, sys
+import sys
 
-# Import build environment variable from SConstruct.
-Import('env')
-
-# Right now there are no source files immediately in this directory
-sources = []
+Import('*')
 
 #################################################################
 #
@@ -47,49 +43,29 @@ sources = []
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-	arguments.hh
-	constants.hh
-	faults.hh
-	isa_traits.hh
-	process.hh
-	regfile.hh
-	stacktrace.hh
-	tlb.hh
-	types.hh
-	utility.hh
-	vtophys.hh
+        arguments.hh
+        faults.hh
+        interrupts.hh
+	isa.hh
+        isa_traits.hh
+        kernel_stats.hh
+        locked_mem.hh
+        microcode_rom.hh
+        mmaped_ipr.hh
+        mt.hh
+        process.hh
+        predecoder.hh
+        registers.hh
+        remote_gdb.hh
+        stacktrace.hh
+        tlb.hh
+        types.hh
+        utility.hh
+        vtophys.hh
         ''')
 
-# Generate the header.  target[0] is the full path of the output
-# header to generate.  'source' is a dummy variable, since we get the
-# list of ISAs from env['ALL_ISA_LIST'].
-def gen_switch_hdr(target, source, env):
-    fname = str(target[0])
-    basename = os.path.basename(fname)
-    f = open(fname, 'w')
-    f.write('#include "arch/isa_specific.hh"\n')
-    cond = '#if'
-    for isa in env['ALL_ISA_LIST']:
-        f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n'
-                % (cond, isa.upper(), isa, basename))
-        cond = '#elif'
-    f.write('#else\n#error "THE_ISA not set"\n#endif\n')
-    f.close()
-    return 0
-
-# String to print when generating header
-def gen_switch_hdr_string(target, source, env):
-    return "Generating ISA switch header " + str(target[0])
-
-# Build SCons Action object. 'varlist' specifies env vars that this
-# action depends on; when env['ALL_ISA_LIST'] changes these actions
-# should get re-executed.
-switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
-                           varlist=['ALL_ISA_LIST'])
-
-# Instantiate actions for each header
-for hdr in isa_switch_hdrs:
-    env.Command(hdr, [], switch_hdr_action)
+# Set up this directory to support switching headers
+make_switching_dir('arch', isa_switch_hdrs, env)
 
 #################################################################
 #
@@ -114,39 +90,43 @@ env.Append(SCANNERS = isa_scanner)
 # output from the ISA description (*.isa) files.
 #
 
-# Convert to File node to fix path
-isa_parser = File('isa_parser.py')
-cpu_models_file = File('../cpu/cpu_models.py')
-
-# This sucks in the defintions of the CpuModel objects.
-execfile(cpu_models_file.srcnode().abspath)
-
-# Several files are generated from the ISA description.
-# We always get the basic decoder and header file.
-isa_desc_gen_files = Split('decoder.cc decoder.hh')
-# We also get an execute file for each selected CPU model.
-isa_desc_gen_files += [CpuModel.dict[cpu].filename
-                       for cpu in env['CPU_MODELS']]
-
 # The emitter patches up the sources & targets to include the
 # autogenerated files as targets and isa parser itself as a source.
 def isa_desc_emitter(target, source, env):
-    return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
+    cpu_models = list(env['CPU_MODELS'])
+    if env['USE_CHECKER']:
+        cpu_models.append('CheckerCPU')
 
-# Pieces are in place, so create the builder.
-python = sys.executable  # use same Python binary used to run scons
-isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
-                           emitter = isa_desc_emitter)
+    # Several files are generated from the ISA description.
+    # We always get the basic decoder and header file.
+    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
+    # We also get an execute file for each selected CPU model.
+    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
 
-env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
+    return target, source + [ Value(m) for m in cpu_models ]
 
-#
-# Now include other ISA-specific sources from the ISA subdirectories.
-#
+ARCH_DIR = Dir('.')
+
+# import ply here because SCons screws with sys.path when performing actions.
+import ply
+
+def isa_desc_action(target, source, env):
+    # Add the current directory to the system path so we can import files
+    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
+    import isa_parser
 
-isa = env['TARGET_ISA'] # someday this may be a list of ISAs
+    models = [ s.get_contents() for s in source[1:] ]
+    cpu_models = [CpuModel.dict[cpu] for cpu in models]
+    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
+    parser.parse_isa_desc(source[0].abspath)
 
-# Let the target architecture define what additional sources it needs
-sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env')
+# Also include the CheckerCPU as one of the models if it is being
+# enabled via command line.
+isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
+
+env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
-Return('sources')
+TraceFlag('IntRegs')
+TraceFlag('FloatRegs')
+TraceFlag('MiscRegs')
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])