X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2FSConscript;h=f271f487f5904c169c424efd6aa71792bca95111;hb=eae1e97fb002b44a9d8c46df2da1ddc1d0156ce4;hp=c90694a68b59295edd5a450f8198542f18f20685;hpb=167fb86a694dbb49fe51cccbb4285bddcbf2cd44;p=gem5.git

diff --git a/src/arch/SConscript b/src/arch/SConscript
index c90694a68..f271f487f 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -28,13 +28,10 @@
 #
 # Authors: Steve Reinhardt
 
-import os.path
+import sys
+import os
 
-# Import build environment variable from SConstruct.
-Import('env')
-
-# Right now there are no source files immediately in this directory
-sources = []
+Import('*')
 
 #################################################################
 #
@@ -47,49 +44,28 @@ sources = []
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-	arguments.hh
-	constants.hh
-	faults.hh
-	isa_traits.hh
-	process.hh
-	regfile.hh
-	stacktrace.hh
-	tlb.hh
-	types.hh
-	utility.hh
-	vtophys.hh
+        decoder.hh
+        interrupts.hh
+        isa.hh
+        isa_traits.hh
+        kernel_stats.hh
+        locked_mem.hh
+        microcode_rom.hh
+        mmapped_ipr.hh
+        mt.hh
+        process.hh
+        predecoder.hh
+        registers.hh
+        remote_gdb.hh
+        stacktrace.hh
+        tlb.hh
+        types.hh
+        utility.hh
+        vtophys.hh
         ''')
 
-# Generate the header.  target[0] is the full path of the output
-# header to generate.  'source' is a dummy variable, since we get the
-# list of ISAs from env['ALL_ISA_LIST'].
-def gen_switch_hdr(target, source, env):
-    fname = str(target[0])
-    basename = os.path.basename(fname)
-    f = open(fname, 'w')
-    f.write('#include "arch/isa_specific.hh"\n')
-    cond = '#if'
-    for isa in env['ALL_ISA_LIST']:
-        f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n'
-                % (cond, isa.upper(), isa, basename))
-        cond = '#elif'
-    f.write('#else\n#error "THE_ISA not set"\n#endif\n')
-    f.close()
-    return 0
-
-# String to print when generating header
-def gen_switch_hdr_string(target, source, env):
-    return "Generating ISA switch header " + str(target[0])
-
-# Build SCons Action object. 'varlist' specifies env vars that this
-# action depends on; when env['ALL_ISA_LIST'] changes these actions
-# should get re-executed.
-switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
-                           varlist=['ALL_ISA_LIST'])
-
-# Instantiate actions for each header
-for hdr in isa_switch_hdrs:
-    env.Command(hdr, [], switch_hdr_action)
+# Set up this directory to support switching headers
+make_switching_dir('arch', isa_switch_hdrs, env)
 
 #################################################################
 #
@@ -114,38 +90,51 @@ env.Append(SCANNERS = isa_scanner)
 # output from the ISA description (*.isa) files.
 #
 
-# Convert to File node to fix path
 isa_parser = File('isa_parser.py')
-cpu_models_file = File('../cpu/cpu_models.py')
-
-# This sucks in the defintions of the CpuModel objects.
-execfile(cpu_models_file.srcnode().abspath)
-
-# Several files are generated from the ISA description.
-# We always get the basic decoder and header file.
-isa_desc_gen_files = Split('decoder.cc decoder.hh')
-# We also get an execute file for each selected CPU model.
-isa_desc_gen_files += [CpuModel.dict[cpu].filename
-                       for cpu in env['CPU_MODELS']]
 
 # The emitter patches up the sources & targets to include the
 # autogenerated files as targets and isa parser itself as a source.
 def isa_desc_emitter(target, source, env):
-    return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
+    cpu_models = list(env['CPU_MODELS'])
+    cpu_models.append('CheckerCPU')
 
-# Pieces are in place, so create the builder.
-isa_desc_builder = Builder(action='python2.4 $SOURCES $TARGET.dir $CPU_MODELS',
-                           emitter = isa_desc_emitter)
+    # Several files are generated from the ISA description.
+    # We always get the basic decoder and header file.
+    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
+    # We also get an execute file for each selected CPU model.
+    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
 
-env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
+    # List the isa parser as a source.
+    source += [ isa_parser ]
+    # Add in the CPU models.
+    source += [ Value(m) for m in cpu_models ]
 
-#
-# Now include other ISA-specific sources from the ISA subdirectories.
-#
+    return [os.path.join("generated", t) for t in target], source
 
-isa = env['TARGET_ISA'] # someday this may be a list of ISAs
+ARCH_DIR = Dir('.')
 
-# Let the target architecture define what additional sources it needs
-sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env')
+# import ply here because SCons screws with sys.path when performing actions.
+import ply
+
+def isa_desc_action_func(target, source, env):
+    # Add the current directory to the system path so we can import files
+    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
+    import isa_parser
+
+    # Skip over the ISA description itself and the parser to the CPU models.
+    models = [ s.get_contents() for s in source[2:] ]
+    cpu_models = [CpuModel.dict[cpu] for cpu in models]
+    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
+    parser.parse_isa_desc(source[0].abspath)
+isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1))
+
+# Also include the CheckerCPU as one of the models if it is being
+# enabled via command line.
+isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
+
+env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
-Return('sources')
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])