X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Farm%2FSConscript;h=08a3c7048968b99bde0ceb296b7f234cbbed642a;hb=0b0c5621eea48a79d1d17e494fa99ea34ad8fad0;hp=ea55314a451fd94ad9ba80799529dd5e68c4abab;hpb=997f36c7115e37f292c50db8986c6ebd4bd1beca;p=gem5.git

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index ea55314a4..08a3c7048 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -1,5 +1,17 @@
 # -*- mode:python -*-
 
+# Copyright (c) 2009 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2007-2008 The Florida State University
 # All rights reserved.
 #
@@ -27,6 +39,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Stephen Hines
+#          Ali Saidi
 
 Import('*')
 
@@ -34,27 +47,40 @@ if env['TARGET_ISA'] == 'arm':
 # Workaround for bug in SCons version > 0.97d20071212
 # Scons bug id: 2006 M5 Bug id: 308 
     Dir('isa/formats')
+    Source('decoder.cc')
     Source('faults.cc')
-    Source('insts/branch.cc')
+    Source('insts/macromem.cc')
     Source('insts/mem.cc')
+    Source('insts/misc.cc')
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
+    Source('insts/vfp.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
-    Source('pagetable.cc')
-    Source('regfile.cc')
+    Source('isa_traits.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
+    Source('miscregs.cc')
+    Source('nativetrace.cc')
+    Source('process.cc')
+    Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
+    Source('table_walker.cc')
     Source('tlb.cc')
+    Source('utility.cc')
     Source('vtophys.cc')
 
+    SimObject('ArmInterrupts.py')
+    SimObject('ArmNativeTrace.py')
+    SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
-    TraceFlag('Arm')
 
-    if env['FULL_SYSTEM']:
-        #Insert Full-System Files Here
-        pass
-    else:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
+    DebugFlag('Arm')
+    DebugFlag('Decoder', "Instructions returned by the predecoder")
+    DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
+    DebugFlag('TLBVerbose')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')