X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Farm%2FSConscript;h=3b68fb64762c228dcfedb2ea0f5c2230d3bea801;hb=b8efd0e854ae568dae33fe3d24f67054ed016d19;hp=fe3d84f6d241b48b81c62d0419bea4daac74fd71;hpb=b2af015b97e609f3e279e9fd050a8b90d4b93233;p=gem5.git

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index fe3d84f6d..3b68fb647 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2009 ARM Limited
+# Copyright (c) 2009, 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -45,49 +45,57 @@ Import('*')
 
 if env['TARGET_ISA'] == 'arm':
 # Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308 
+# Scons bug id: 2006 M5 Bug id: 308
     Dir('isa/formats')
+    Source('decoder.cc')
     Source('faults.cc')
+    Source('insts/branch64.cc')
+    Source('insts/data64.cc')
     Source('insts/macromem.cc')
     Source('insts/mem.cc')
+    Source('insts/mem64.cc')
     Source('insts/misc.cc')
+    Source('insts/misc64.cc')
     Source('insts/pred_inst.cc')
+    Source('insts/pseudo.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
+    Source('insts/fplib.cc')
     Source('interrupts.cc')
     Source('isa.cc')
+    Source('isa_device.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
+    Source('freebsd/freebsd.cc')
+    Source('freebsd/process.cc')
+    Source('freebsd/system.cc')
     Source('miscregs.cc')
-    Source('predecoder.cc')
     Source('nativetrace.cc')
+    Source('pmu.cc')
+    Source('process.cc')
+    Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
     Source('table_walker.cc')
+    Source('stage2_mmu.cc')
+    Source('stage2_lookup.cc')
     Source('tlb.cc')
     Source('utility.cc')
-    Source('remote_gdb.cc')
+    Source('vtophys.cc')
 
     SimObject('ArmInterrupts.py')
+    SimObject('ArmISA.py')
     SimObject('ArmNativeTrace.py')
+    SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
+    SimObject('ArmPMU.py')
 
     DebugFlag('Arm')
-    DebugFlag('TLBVerbose')
+    DebugFlag('Decoder', "Instructions returned by the predecoder")
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
-    DebugFlag('Predecoder', "Instructions returned by the predecoder")
-    if env['FULL_SYSTEM']:
-        Source('stacktrace.cc')
-        Source('system.cc')
-        Source('vtophys.cc')
-        Source('linux/system.cc')
-        
-        SimObject('ArmSystem.py')
-    else:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
-
-    # Add in files generated by the ISA description.
-    isa_desc_files = env.ISADesc('isa/main.isa')
-    # Only non-header files need to be compiled.
-    for f in isa_desc_files:
-        if not f.path.endswith('.hh'):
-            Source(f)
+    DebugFlag('PMUVerbose', "Performance Monitor")
+    DebugFlag('TLBVerbose')
 
+    # Add files generated by the ISA description.
+    ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)