X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fisa_parser.py;h=ec0efe5e6a95c8ec806e9df5877b1106c286aa7c;hb=d2fd3b2ec2c265eb9ed3bdcc1db3e4c3feee3846;hp=947742354ba16a36dbfdbaaa89fe19b9bad1aed6;hpb=57ed5e77fe8366d680768189f8d3c67f8413879a;p=gem5.git diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 947742354..ec0efe5e6 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -174,6 +174,16 @@ class Template(object): if operands.readPC or operands.setPC: myDict['op_decl'] += 'TheISA::PCState __parserAutoPCState;\n' + # In case there are predicated register reads and write, declare + # the variables for register indicies. It is being assumed that + # all the operands in the OperandList are also in the + # SubOperandList and in the same order. Otherwise, it is + # expected that predication would not be used for the operands. + if operands.predRead: + myDict['op_decl'] += 'uint8_t _sourceIndex = 0;\n' + if operands.predWrite: + myDict['op_decl'] += 'uint8_t M5_VAR_USED _destIndex = 0;\n' + is_src = lambda op: op.is_src is_dest = lambda op: op.is_dest @@ -209,10 +219,6 @@ class Template(object): op_wb_str = op_desc.op_wb + op_wb_str myDict['op_wb'] = op_wb_str - if d.operands.memOperand: - myDict['mem_acc_size'] = d.operands.memOperand.mem_acc_size - myDict['mem_acc_type'] = d.operands.memOperand.mem_acc_type - elif isinstance(d, dict): # if the argument is a dictionary, we just use it. myDict.update(d) @@ -417,29 +423,18 @@ class Operand(object): subst_dict = {"name": self.base_name, "func": func, "reg_idx": self.reg_spec, - "size": self.size, "ctype": self.ctype} if hasattr(self, 'src_reg_idx'): subst_dict['op_idx'] = self.src_reg_idx code = self.read_code % subst_dict - if self.size != self.dflt_size: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, code, self.size-1) - else: - return '%s = %s;\n' % \ - (self.base_name, code) + return '%s = %s;\n' % (self.base_name, code) def buildWriteCode(self, func = None): - if (self.size != self.dflt_size and self.is_signed): - final_val = 'sext<%d>(%s)' % (self.size, self.base_name) - else: - final_val = self.base_name subst_dict = {"name": self.base_name, "func": func, "reg_idx": self.reg_spec, - "size": self.size, "ctype": self.ctype, - "final_val": final_val} + "final_val": self.base_name} if hasattr(self, 'dest_reg_idx'): subst_dict['op_idx'] = self.dest_reg_idx code = self.write_code % subst_dict @@ -448,7 +443,7 @@ class Operand(object): %s final_val = %s; %s; if (traceData) { traceData->setData(final_val); } - }''' % (self.dflt_ctype, final_val, code) + }''' % (self.dflt_ctype, self.base_name, code) def __init__(self, parser, full_name, ext, is_src, is_dest): self.full_name = full_name @@ -463,36 +458,28 @@ class Operand(object): self.eff_ext = self.dflt_ext if hasattr(self, 'eff_ext'): - self.size, self.ctype, self.is_signed = \ - parser.operandTypeMap[self.eff_ext] - - # note that mem_acc_size is undefined for non-mem operands... - # template must be careful not to use it if it doesn't apply. - if self.isMem(): - self.mem_acc_size = self.makeAccSize() - if self.ctype in ['Twin32_t', 'Twin64_t']: - self.mem_acc_type = 'Twin' - else: - self.mem_acc_type = 'uint' + self.ctype = parser.operandTypeMap[self.eff_ext] # Finalize additional fields (primarily code fields). This step # is done separately since some of these fields may depend on the # register index enumeration that hasn't been performed yet at the - # time of __init__(). - def finalize(self): + # time of __init__(). The register index enumeration is affected + # by predicated register reads/writes. Hence, we forward the flags + # that indicate whether or not predication is in use. + def finalize(self, predRead, predWrite): self.flags = self.getFlags() - self.constructor = self.makeConstructor() + self.constructor = self.makeConstructor(predRead, predWrite) self.op_decl = self.makeDecl() if self.is_src: - self.op_rd = self.makeRead() + self.op_rd = self.makeRead(predRead) self.op_src_decl = self.makeDecl() else: self.op_rd = '' self.op_src_decl = '' if self.is_dest: - self.op_wb = self.makeWrite() + self.op_wb = self.makeWrite(predWrite) self.op_dest_decl = self.makeDecl() else: self.op_wb = '' @@ -519,6 +506,12 @@ class Operand(object): def isPCPart(self): return self.isPCState() and self.reg_spec + def hasReadPred(self): + return self.read_predicate != None + + def hasWritePred(self): + return self.write_predicate != None + def getFlags(self): # note the empty slice '[:]' gives us a copy of self.flags[0] # instead of a reference to it @@ -541,49 +534,68 @@ class IntRegOperand(Operand): def isIntReg(self): return 1 - def makeConstructor(self): - c = '' + def makeConstructor(self, predRead, predWrite): + c_src = '' + c_dest = '' + if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s;' % \ - (self.src_reg_idx, self.reg_spec) + c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s;' % (self.reg_spec) + if self.hasReadPred(): + c_src = '\n\tif (%s) {%s\n\t}' % \ + (self.read_predicate, c_src) + if self.is_dest: - c += '\n\t_destRegIdx[%d] = %s;' % \ - (self.dest_reg_idx, self.reg_spec) - return c + c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s;' % \ + (self.reg_spec) + c_dest += '\n\t_numIntDestRegs++;' + if self.hasWritePred(): + c_dest = '\n\tif (%s) {%s\n\t}' % \ + (self.write_predicate, c_dest) + + return c_src + c_dest - def makeRead(self): + def makeRead(self, predRead): if (self.ctype == 'float' or self.ctype == 'double'): error('Attempt to read integer register as FP') if self.read_code != None: return self.buildReadCode('readIntRegOperand') - if (self.size == self.dflt_size): - return '%s = xc->readIntRegOperand(this, %d);\n' % \ - (self.base_name, self.src_reg_idx) - elif (self.size > self.dflt_size): - int_reg_val = 'xc->readIntRegOperand(this, %d)' % \ - (self.src_reg_idx) - if (self.is_signed): - int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val) - return '%s = %s;\n' % (self.base_name, int_reg_val) + + int_reg_val = '' + if predRead: + int_reg_val = 'xc->readIntRegOperand(this, _sourceIndex++)' + if self.hasReadPred(): + int_reg_val = '(%s) ? %s : 0' % \ + (self.read_predicate, int_reg_val) else: - return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \ - (self.base_name, self.src_reg_idx, self.size-1) + int_reg_val = 'xc->readIntRegOperand(this, %d)' % self.src_reg_idx + + return '%s = %s;\n' % (self.base_name, int_reg_val) - def makeWrite(self): + def makeWrite(self, predWrite): if (self.ctype == 'float' or self.ctype == 'double'): error('Attempt to write integer register as FP') if self.write_code != None: return self.buildWriteCode('setIntRegOperand') - if (self.size != self.dflt_size and self.is_signed): - final_val = 'sext<%d>(%s)' % (self.size, self.base_name) + + if predWrite: + wp = 'true' + if self.hasWritePred(): + wp = self.write_predicate + + wcond = 'if (%s)' % (wp) + windex = '_destIndex++' else: - final_val = self.base_name + wcond = '' + windex = '%d' % self.dest_reg_idx + wb = ''' + %s { %s final_val = %s; - xc->setIntRegOperand(this, %d, final_val);\n + xc->setIntRegOperand(this, %s, final_val);\n if (traceData) { traceData->setData(final_val); } - }''' % (self.dflt_ctype, final_val, self.dest_reg_idx) + }''' % (wcond, self.ctype, self.base_name, windex) + return wb class FloatRegOperand(Operand): @@ -593,53 +605,59 @@ class FloatRegOperand(Operand): def isFloatReg(self): return 1 - def makeConstructor(self): - c = '' + def makeConstructor(self, predRead, predWrite): + c_src = '' + c_dest = '' + if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s + FP_Base_DepTag;' % \ - (self.src_reg_idx, self.reg_spec) + c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;' % \ + (self.reg_spec) + if self.is_dest: - c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \ - (self.dest_reg_idx, self.reg_spec) - return c + c_dest = \ + '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Base_DepTag;' % \ + (self.reg_spec) + c_dest += '\n\t_numFPDestRegs++;' + + return c_src + c_dest - def makeRead(self): + def makeRead(self, predRead): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): func = 'readFloatRegOperand' else: func = 'readFloatRegOperandBits' - if (self.size != self.dflt_size): - bit_select = 1 - base = 'xc->%s(this, %d)' % (func, self.src_reg_idx) if self.read_code != None: return self.buildReadCode(func) - if bit_select: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, base, self.size-1) + + if predRead: + rindex = '_sourceIndex++' else: - return '%s = %s;\n' % (self.base_name, base) + rindex = '%d' % self.src_reg_idx + + return '%s = xc->%s(this, %s);\n' % \ + (self.base_name, func, rindex) - def makeWrite(self): - final_val = self.base_name - final_ctype = self.ctype + def makeWrite(self, predWrite): if (self.ctype == 'float' or self.ctype == 'double'): func = 'setFloatRegOperand' - elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'): - func = 'setFloatRegOperandBits' else: func = 'setFloatRegOperandBits' - final_ctype = 'uint%d_t' % self.dflt_size - if (self.size != self.dflt_size and self.is_signed): - final_val = 'sext<%d>(%s)' % (self.size, self.base_name) if self.write_code != None: return self.buildWriteCode(func) + + if predWrite: + wp = '_destIndex++' + else: + wp = '%d' % self.dest_reg_idx + wp = 'xc->%s(this, %s, final_val);' % (func, wp) + wb = ''' { %s final_val = %s; - xc->%s(this, %d, final_val);\n + %s\n if (traceData) { traceData->setData(final_val); } - }''' % (final_ctype, final_val, func, self.dest_reg_idx) + }''' % (self.ctype, self.base_name, wp) return wb class ControlRegOperand(Operand): @@ -649,76 +667,83 @@ class ControlRegOperand(Operand): def isControlReg(self): return 1 - def makeConstructor(self): - c = '' + def makeConstructor(self, predRead, predWrite): + c_src = '' + c_dest = '' + if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ - (self.src_reg_idx, self.reg_spec) + c_src = \ + '\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;' % \ + (self.reg_spec) + if self.is_dest: - c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ - (self.dest_reg_idx, self.reg_spec) - return c + c_dest = \ + '\n\t_destRegIdx[_numDestRegs++] = %s + Ctrl_Base_DepTag;' % \ + (self.reg_spec) + + return c_src + c_dest - def makeRead(self): + def makeRead(self, predRead): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error('Attempt to read control register as FP') if self.read_code != None: return self.buildReadCode('readMiscRegOperand') - base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx - if self.size == self.dflt_size: - return '%s = %s;\n' % (self.base_name, base) + + if predRead: + rindex = '_sourceIndex++' else: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, base, self.size-1) + rindex = '%d' % self.src_reg_idx - def makeWrite(self): + return '%s = xc->readMiscRegOperand(this, %s);\n' % \ + (self.base_name, rindex) + + def makeWrite(self, predWrite): if (self.ctype == 'float' or self.ctype == 'double'): error('Attempt to write control register as FP') if self.write_code != None: return self.buildWriteCode('setMiscRegOperand') + + if predWrite: + windex = '_destIndex++' + else: + windex = '%d' % self.dest_reg_idx + wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ - (self.dest_reg_idx, self.base_name) + (windex, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name + return wb class MemOperand(Operand): def isMem(self): return 1 - def makeConstructor(self): + def makeConstructor(self, predRead, predWrite): return '' def makeDecl(self): # Note that initializations in the declarations are solely # to avoid 'uninitialized variable' errors from the compiler. # Declare memory data variable. - if self.ctype in ['Twin32_t','Twin64_t']: - return "%s %s; %s.a = 0; %s.b = 0;\n" % \ - (self.ctype, self.base_name, self.base_name, self.base_name) return '%s %s = 0;\n' % (self.ctype, self.base_name) - def makeRead(self): + def makeRead(self, predRead): if self.read_code != None: return self.buildReadCode() return '' - def makeWrite(self): + def makeWrite(self, predWrite): if self.write_code != None: return self.buildWriteCode() return '' - # Return the memory access size *in bits*, suitable for - # forming a type via "uint%d_t". Divide by 8 if you want bytes. - def makeAccSize(self): - return self.size - class PCStateOperand(Operand): - def makeConstructor(self): + def makeConstructor(self, predRead, predWrite): return '' - def makeRead(self): + def makeRead(self, predRead): if self.reg_spec: # A component of the PC state. return '%s = __parserAutoPCState.%s();\n' % \ @@ -727,7 +752,7 @@ class PCStateOperand(Operand): # The whole PC state itself. return '%s = xc->pcState();\n' % self.base_name - def makeWrite(self): + def makeWrite(self, predWrite): if self.reg_spec: # A component of the PC state. return '__parserAutoPCState.%s(%s);\n' % \ @@ -751,8 +776,9 @@ class OperandList(object): def __init__(self, parser, code): self.items = [] self.bases = {} - # delete comments so we don't match on reg specifiers inside - code = commentRE.sub('', code) + # delete strings and comments so we don't match on operands inside + for regEx in (stringRE, commentRE): + code = regEx.sub('', code) # search for operands next_pos = 0 while 1: @@ -789,7 +815,14 @@ class OperandList(object): self.numDestRegs = 0 self.numFPDestRegs = 0 self.numIntDestRegs = 0 + self.numMiscDestRegs = 0 self.memOperand = None + + # Flags to keep track if one or more operands are to be read/written + # conditionally. + self.predRead = False + self.predWrite = False + for op_desc in self.items: if op_desc.isReg(): if op_desc.is_src: @@ -802,18 +835,29 @@ class OperandList(object): self.numFPDestRegs += 1 elif op_desc.isIntReg(): self.numIntDestRegs += 1 + elif op_desc.isControlReg(): + self.numMiscDestRegs += 1 elif op_desc.isMem(): if self.memOperand: error("Code block has more than one memory operand.") self.memOperand = op_desc + + # Check if this operand has read/write predication. If true, then + # the microop will dynamically index source/dest registers. + self.predRead = self.predRead or op_desc.hasReadPred() + self.predWrite = self.predWrite or op_desc.hasWritePred() + if parser.maxInstSrcRegs < self.numSrcRegs: parser.maxInstSrcRegs = self.numSrcRegs if parser.maxInstDestRegs < self.numDestRegs: parser.maxInstDestRegs = self.numDestRegs + if parser.maxMiscDestRegs < self.numMiscDestRegs: + parser.maxMiscDestRegs = self.numMiscDestRegs + # now make a final pass to finalize op_desc fields that may depend # on the register enumeration for op_desc in self.items: - op_desc.finalize() + op_desc.finalize(self.predRead, self.predWrite) def __len__(self): return len(self.items) @@ -866,8 +910,9 @@ class SubOperandList(OperandList): def __init__(self, parser, code, master_list): self.items = [] self.bases = {} - # delete comments so we don't match on reg specifiers inside - code = commentRE.sub('', code) + # delete strings and comments so we don't match on operands inside + for regEx in (stringRE, commentRE): + code = regEx.sub('', code) # search for operands next_pos = 0 while 1: @@ -902,25 +947,42 @@ class SubOperandList(OperandList): # Whether this instruction manipulates the whole PC or parts of it. # Mixing the two is a bad idea and flagged as an error. self.pcPart = None + + # Flags to keep track if one or more operands are to be read/written + # conditionally. + self.predRead = False + self.predWrite = False + for op_desc in self.items: if op_desc.isPCPart(): self.readPC = True if op_desc.is_dest: self.setPC = True + if op_desc.isPCState(): if self.pcPart is not None: if self.pcPart and not op_desc.isPCPart() or \ not self.pcPart and op_desc.isPCPart(): error("Mixed whole and partial PC state operands.") self.pcPart = op_desc.isPCPart() + if op_desc.isMem(): if self.memOperand: error("Code block has more than one memory operand.") self.memOperand = op_desc + # Check if this operand has read/write predication. If true, then + # the microop will dynamically index source/dest registers. + self.predRead = self.predRead or op_desc.hasReadPred() + self.predWrite = self.predWrite or op_desc.hasWritePred() + +# Regular expression object to match C++ strings +stringRE = re.compile(r'"([^"\\]|\\.)*"') + # Regular expression object to match C++ comments # (used in findOperands()) -commentRE = re.compile(r'//.*\n') +commentRE = re.compile(r'(^)?[^\S\n]*/(?:\*(.*?)\*/[^\S\n]*|/[^\n]*)($)?', + re.DOTALL | re.MULTILINE) # Regular expression object to match assignment statements # (used in findOperands()) @@ -960,15 +1022,18 @@ class InstObjParams(object): self.snippets = snippets self.operands = OperandList(parser, compositeCode) - self.constructor = self.operands.concatAttrStrings('constructor') - self.constructor += \ - '\n\t_numSrcRegs = %d;' % self.operands.numSrcRegs - self.constructor += \ - '\n\t_numDestRegs = %d;' % self.operands.numDestRegs - self.constructor += \ - '\n\t_numFPDestRegs = %d;' % self.operands.numFPDestRegs - self.constructor += \ - '\n\t_numIntDestRegs = %d;' % self.operands.numIntDestRegs + + # The header of the constructor declares the variables to be used + # in the body of the constructor. + header = '' + header += '\n\t_numSrcRegs = 0;' + header += '\n\t_numDestRegs = 0;' + header += '\n\t_numFPDestRegs = 0;' + header += '\n\t_numIntDestRegs = 0;' + + self.constructor = header + \ + self.operands.concatAttrStrings('constructor') + self.flags = self.operands.concatAttrLists('flags') # Make a basic guess on the operand class (function unit type). @@ -1059,6 +1124,7 @@ namespace %(namespace)s { const int MaxInstSrcRegs = %(MaxInstSrcRegs)d; const int MaxInstDestRegs = %(MaxInstDestRegs)d; + const int MaxMiscDestRegs = %(MaxMiscDestRegs)d; } // namespace %(namespace)s @@ -1094,6 +1160,7 @@ class ISAParser(Grammar): self.maxInstSrcRegs = 0 self.maxInstDestRegs = 0 + self.maxMiscDestRegs = 0 ##################################################################### # @@ -1215,7 +1282,7 @@ class ISAParser(Grammar): return t def t_NEWFILE(self, t): - r'^\#\#newfile\s+"[\w/.-]*"' + r'^\#\#newfile\s+"[^"]*"' self.fileNameStack.push((t.value[11:-1], t.lexer.lineno)) t.lexer.lineno = 0 @@ -1276,7 +1343,7 @@ class ISAParser(Grammar): # wrap the decode block as a function definition t[4].wrap_decode_block(''' StaticInstPtr -%(isa_name)s::decodeInst(%(isa_name)s::ExtMachInst machInst) +%(isa_name)s::Decoder::decodeInst(%(isa_name)s::ExtMachInst machInst) { using namespace %(namespace)s; ''' % vars(), '}') @@ -1377,13 +1444,12 @@ StaticInstPtr def p_def_operand_types(self, t): 'def_operand_types : DEF OPERAND_TYPES CODELIT SEMI' try: - user_dict = eval('{' + t[3] + '}') + self.operandTypeMap = eval('{' + t[3] + '}') except Exception, exc: if debug: raise error(t, 'error: %s in def operand_types block "%s".' % (exc, t[3])) - self.buildOperandTypeMap(user_dict, t.lexer.lineno) t[0] = GenCode(self) # contributes nothing to the output C++ file # Define the mapping from operand names to operand classes and @@ -1844,53 +1910,20 @@ StaticInstPtr return re.sub(r'%(?!\()', '%%', s) - def buildOperandTypeMap(self, user_dict, lineno): - """Generate operandTypeMap from the user's 'def operand_types' - statement.""" - operand_type = {} - for (ext, (desc, size)) in user_dict.iteritems(): - if desc == 'signed int': - ctype = 'int%d_t' % size - is_signed = 1 - elif desc == 'unsigned int': - ctype = 'uint%d_t' % size - is_signed = 0 - elif desc == 'float': - is_signed = 1 # shouldn't really matter - if size == 32: - ctype = 'float' - elif size == 64: - ctype = 'double' - elif desc == 'twin64 int': - is_signed = 0 - ctype = 'Twin64_t' - elif desc == 'twin32 int': - is_signed = 0 - ctype = 'Twin32_t' - if ctype == '': - error(parser, lineno, - 'Unrecognized type description "%s" in user_dict') - operand_type[ext] = (size, ctype, is_signed) - - self.operandTypeMap = operand_type - def buildOperandNameMap(self, user_dict, lineno): operand_name = {} for op_name, val in user_dict.iteritems(): - base_cls_name, dflt_ext, reg_spec, flags, sort_pri = val[:5] - if len(val) > 5: - read_code = val[5] - else: - read_code = None - if len(val) > 6: - write_code = val[6] - else: - write_code = None - if len(val) > 7: - error(lineno, - 'error: too many attributes for operand "%s"' % + + # Check if extra attributes have been specified. + if len(val) > 9: + error(lineno, 'error: too many attributes for operand "%s"' % base_cls_name) + # Pad val with None in case optional args are missing + val += (None, None, None, None) + base_cls_name, dflt_ext, reg_spec, flags, sort_pri, \ + read_code, write_code, read_predicate, write_predicate = val[:9] + # Canonical flag structure is a triple of lists, where each list # indicates the set of flags implied by this operand always, when # used as a source, and when used as a dest, respectively. @@ -1911,18 +1944,19 @@ StaticInstPtr (uncond_flags, src_flags, dest_flags) = flags flags = (makeList(uncond_flags), makeList(src_flags), makeList(dest_flags)) + # Accumulate attributes of new operand class in tmp_dict tmp_dict = {} attrList = ['reg_spec', 'flags', 'sort_pri', - 'read_code', 'write_code'] + 'read_code', 'write_code', + 'read_predicate', 'write_predicate'] if dflt_ext: - (dflt_size, dflt_ctype, dflt_is_signed) = \ - self.operandTypeMap[dflt_ext] - attrList.extend(['dflt_size', 'dflt_ctype', - 'dflt_is_signed', 'dflt_ext']) + dflt_ctype = self.operandTypeMap[dflt_ext] + attrList.extend(['dflt_ctype', 'dflt_ext']) for attr in attrList: tmp_dict[attr] = eval(attr) tmp_dict['base_name'] = op_name + # New class name will be e.g. "IntReg_Ra" cls_name = base_cls_name + '_' + op_name # Evaluate string arg to get class object. Note that the @@ -1942,21 +1976,21 @@ StaticInstPtr # Define operand variables. operands = user_dict.keys() + extensions = self.operandTypeMap.keys() - operandsREString = (r''' - (?[\w/.-]*)".*$', + includeRE = re.compile(r'^\s*##include\s+"(?P[^"]*)".*$', re.MULTILINE) def replace_include(self, matchobj, dirname): @@ -2046,7 +2080,7 @@ StaticInstPtr # Parse it. (isa_name, namespace, global_code, namespace_code) = \ - self.parse(isa_desc) + self.parse_string(isa_desc) # grab the last three path components of isa_desc_file to put in # the output @@ -2081,6 +2115,7 @@ StaticInstPtr # value of the globals. MaxInstSrcRegs = self.maxInstSrcRegs MaxInstDestRegs = self.maxInstDestRegs + MaxMiscDestRegs = self.maxMiscDestRegs # max_inst_regs.hh self.update_if_needed('max_inst_regs.hh', max_inst_regs_template % vars())