X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fmips%2Fisa%2Fformats%2Ffp.isa;h=59dba687006998cec9ca27dcfdc8d667764c0aaf;hb=5edfb67041ad1c246f4ceca147f06b9db3c0ecc3;hp=2506e18641f8de20f35e46ea4ad833f601cc0bdf;hpb=3fd291bc4ec0934f51137f1ba1f253f7093c2d88;p=gem5.git diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 2506e1864..59dba6870 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -1,38 +1,32 @@ // -*- mode:c++ -*- -// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved - -// This software is part of the M5 simulator. - -// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING -// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING -// TO THESE TERMS AND CONDITIONS. - -// Permission is granted to use, copy, create derivative works and -// distribute this software and such derivative works for any purpose, -// so long as (1) the copyright notice above, this grant of permission, -// and the disclaimer below appear in all copies and derivative works -// made, (2) the copyright notice above is augmented as appropriate to -// reflect the addition of any new copyrightable work in a derivative -// work (e.g., Copyright N) Copyright Owner), and (3) -// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any -// advertising or publicity pertaining to the use or distribution of -// this software without specific, written prior authorization. - -// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND -// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR -// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND -// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. -// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, -// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF -// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, -// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY -// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR -// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE -// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. - -//Authors: Korey L. Sewell +// Copyright (c) 2007 MIPS Technologies, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Korey Sewell //////////////////////////////////////////////////////////////////// // @@ -52,8 +46,6 @@ output header {{ { } - //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - //needs function to check for fpEnable or not }; @@ -64,8 +56,8 @@ output header {{ { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; }}; @@ -92,13 +84,18 @@ output decoder {{ } }}; +output header {{ + void fpResetCauseBits(ExecContext *cpu); + +}}; + output exec {{ - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + inline Fault checkFpEnableFault(ExecContext *xc) { //@TODO: Implement correct CP0 checks to see if the CP1 // unit is enable or not if (!isCoprocessorEnabled(xc, 1)) - return new CoprocessorUnusableFault(1); + return std::make_shared(1); return NoFault; } @@ -106,29 +103,18 @@ output exec {{ //If any operand is Nan return the appropriate QNaN template bool - fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, + fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type, Trace::InstRecord *traceData) { uint64_t mips_nan = 0; - T src_op = 0; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); for (int i = 0; i < inst->numSrcRegs(); i++) { - uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); - - if (isNan(&src_bits, size) ) { - if (isSnan(&src_bits, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } - } else { - mips_nan = src_bits; - } + uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); - xc->setFloatRegOperandBits(inst, 0, mips_nan, size); + if (isNan(&src_bits, 32) ) { + mips_nan = MIPS32_QNAN; + xc->setFloatRegOperandBits(inst, 0, mips_nan); if (traceData) { traceData->setData(mips_nan); } return true; } @@ -138,31 +124,27 @@ output exec {{ template bool - fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, + fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val, Trace::InstRecord *traceData) { uint64_t mips_nan = 0; T src_op = dest_val; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); - if (isNan(&src_op, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } + if (isNan(&src_op, 32)) { + mips_nan = MIPS32_QNAN; //Set value to QNAN - cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); + cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile - uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr_bits = + cpu->tcBase()->readFloatReg(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -172,21 +154,22 @@ output exec {{ } void - fpResetCauseBits(%(CPU_exec_context)s *cpu) + fpResetCauseBits(ExecContext *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, fcsr); + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr); } }}; def template FloatingPointExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -195,9 +178,8 @@ def template FloatingPointExecute {{ //When is the right time to reset cause bits? //start of every instruction or every cycle? -#if FULL_SYSTEM - fpResetCauseBits(xc); -#endif + if (FullSystem) + fpResetCauseBits(xc); %(op_decl)s; %(op_rd)s; @@ -212,12 +194,12 @@ def template FloatingPointExecute {{ //---- //Check for IEEE 754 FP Exceptions //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); - if ( -#if FULL_SYSTEM - !fpInvalidOp((FPOp*)this, xc, Fd, traceData) && -#endif - fault == NoFault) - { + bool invalid_op = false; + if (FullSystem) { + invalid_op = + fpInvalidOp((FPOp*)this, xc, Fd, traceData); + } + if (!invalid_op && fault == NoFault) { %(op_wb)s; } } @@ -239,20 +221,20 @@ def format FloatCompareOp(cond_code, *flags) {{ import sys code = 'bool cond;\n' - if '.sf' in cond_code or 'SinglePrecision' in flags: + if '_sf' in cond_code or 'SinglePrecision' in flags: if 'QnanException' in flags: - code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' + code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\treturn NoFault;' code += '}\n else ' - code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' - elif '.df' in cond_code or 'DoublePrecision' in flags: + code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n' + elif '_df' in cond_code or 'DoublePrecision' in flags: if 'QnanException' in flags: - code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' + code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\treturn NoFault;' code += '}\n else ' - code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' + code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n' else: sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') @@ -279,30 +261,30 @@ def format FloatConvertOp(code, *flags) {{ #Determine Source Type convert = 'fpConvert(' - if '.sf' in code: + if '_sf' in code: code = 'float ' + code + '\n' convert += 'SINGLE_TO_' - elif '.df' in code: + elif '_df' in code: code = 'double ' + code + '\n' convert += 'DOUBLE_TO_' - elif '.uw' in code: - code = 'uint32_t ' + code + '\n' + elif '_sw' in code: + code = 'int32_t ' + code + '\n' convert += 'WORD_TO_' - elif '.ud' in code: - code = 'uint64_t ' + code + '\n' + elif '_sd' in code: + code = 'int64_t ' + code + '\n' convert += 'LONG_TO_' else: sys.exit("Error Determining Source Type for Conversion") #Determine Destination Type if 'ToSingle' in flags: - code += 'Fd.uw = ' + convert + 'SINGLE, ' + code += 'Fd_uw = ' + convert + 'SINGLE, ' elif 'ToDouble' in flags: - code += 'Fd.ud = ' + convert + 'DOUBLE, ' + code += 'Fd_ud = ' + convert + 'DOUBLE, ' elif 'ToWord' in flags: - code += 'Fd.uw = ' + convert + 'WORD, ' + code += 'Fd_uw = ' + convert + 'WORD, ' elif 'ToLong' in flags: - code += 'Fd.ud = ' + convert + 'LONG, ' + code += 'Fd_ud = ' + convert + 'LONG, ' else: sys.exit("Error Determining Destination Type for Conversion") @@ -350,17 +332,17 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ code += 'code_block1 = code_block2 = true;\n' if 'QnanException' in flags: - code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' + code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += 'code_block1 = false;' code += '}\n' - code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' + code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += 'code_block2 = false;' code += '}\n' code += 'if (code_block1) {' - code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' + code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n' if 'UnorderedTrue' in flags: code += 'cond1 = 1;\n' elif 'UnorderedFalse' in flags: @@ -372,7 +354,7 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' code += 'if (code_block2) {' - code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' + code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n' if 'UnorderedTrue' in flags: code += 'cond2 = 1;\n' elif 'UnorderedFalse' in flags: