X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fpower%2Finsts%2Fbranch.cc;h=fce3d3f64827706fb570354327e77cb548416a0d;hb=c9111802872744a62d99eb41b5ef181135b3b626;hp=4b75997bc373a3b72963a54c89c88db9c8e5986b;hpb=31e9714364dba399bf0a5243b342e6efe9088669;p=gem5.git

diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 4b75997bc..fce3d3f64 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -34,7 +34,8 @@
 using namespace PowerISA;
 
 const std::string &
-PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const
+PCDependentDisassembly::disassemble(
+        Addr pc, const Loader::SymbolTable *symtab) const
 {
     if (!cachedDisassembly ||
         pc != cachedPC || symtab != cachedSymtab)
@@ -51,119 +52,114 @@ PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const
     return *cachedDisassembly;
 }
 
-PowerISA::PCState
-BranchPCRel::branchTarget(const PowerISA::PCState &pc) const
-{
-    return (uint32_t)(pc.pc() + disp);
-}
-
-std::string
-BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-    std::stringstream ss;
-
-    ccprintf(ss, "%-10s ", mnemonic);
-
-    Addr target = pc + disp;
-
-    std::string str;
-    if (symtab && symtab->findSymbol(target, str))
-        ss << str;
-    else
-        ccprintf(ss, "0x%x", target);
-
-    return ss.str();
-}
 
 PowerISA::PCState
-BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const
-{
-    return targetAddr;
-}
-
-std::string
-BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+BranchOp::branchTarget(const PowerISA::PCState &pc) const
 {
-    std::stringstream ss;
-
-    ccprintf(ss, "%-10s ", mnemonic);
-
-    std::string str;
-    if (symtab && symtab->findSymbol(targetAddr, str))
-        ss << str;
-    else
-        ccprintf(ss, "0x%x", targetAddr);
-
-    return ss.str();
+    if (aaSet) {
+        return disp;
+    } else {
+        return pc.pc() + disp;
+    }
 }
 
-PowerISA::PCState
-BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const
-{
-    return (uint32_t)(pc.pc() + disp);
-}
 
 std::string
-BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+BranchOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
+    Addr target;
 
-    ccprintf(ss, "%-10s ", mnemonic);
+    // Generate correct mnemonic
+    std::string myMnemonic(mnemonic);
 
-    ss << bo << ", " << bi << ", ";
+    // Additional characters depending on isa bits being set
+    if (lkSet) myMnemonic = myMnemonic + "l";
+    if (aaSet) myMnemonic = myMnemonic + "a";
+    ccprintf(ss, "%-10s ", myMnemonic);
 
-    Addr target = pc + disp;
+    if (aaSet) {
+        target = disp;
+    } else {
+        target = pc + disp;
+    }
 
-    std::string str;
-    if (symtab && symtab->findSymbol(target, str))
-        ss << str;
+    Loader::SymbolTable::const_iterator it;
+    if (symtab && (it = symtab->find(target)) != symtab->end())
+        ss << it->name;
     else
-        ccprintf(ss, "0x%x", target);
+        ccprintf(ss, "%#x", target);
 
     return ss.str();
 }
 
+
 PowerISA::PCState
-BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const
+BranchDispCondOp::branchTarget(const PowerISA::PCState &pc) const
 {
-    return targetAddr;
+    if (aaSet) {
+        return disp;
+    } else {
+        return pc.pc() + disp;
+    }
 }
 
+
 std::string
-BranchNonPCRelCond::generateDisassembly(Addr pc,
-                                        const SymbolTable *symtab) const
+BranchDispCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
+    Addr target;
 
-    ccprintf(ss, "%-10s ", mnemonic);
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Additional characters depending on isa bits being set
+    if (lkSet) myMnemonic = myMnemonic + "l";
+    if (aaSet) myMnemonic = myMnemonic + "a";
+    ccprintf(ss, "%-10s ", myMnemonic);
 
-    ss << bo << ", " << bi << ", ";
+    // Print BI and BO fields
+    ss << crBit << ", " << opts << ", ";
 
-    std::string str;
-    if (symtab && symtab->findSymbol(targetAddr, str))
-        ss << str;
+    if (aaSet) {
+        target = disp;
+    } else {
+        target = pc + disp;
+    }
+
+    Loader::SymbolTable::const_iterator it;
+    if (symtab && (it = symtab->find(target)) != symtab->end())
+        ss << it->name;
     else
-        ccprintf(ss, "0x%x", targetAddr);
+        ccprintf(ss, "%#x", target);
 
     return ss.str();
 }
 
+
 PowerISA::PCState
-BranchRegCond::branchTarget(ThreadContext *tc) const
+BranchRegCondOp::branchTarget(ThreadContext *tc) const
 {
-    uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
-    return regVal & 0xfffffffc;
+    Addr addr = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
+    return addr & -4ULL;
 }
 
+
 std::string
-BranchRegCond::generateDisassembly(Addr pc,
-                                   const SymbolTable *symtab) const
+BranchRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
 
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Additional characters depending on isa bits being set
+    if (lkSet) myMnemonic = myMnemonic + "l";
     ccprintf(ss, "%-10s ", mnemonic);
 
-    ss << bo << ", " << bi << ", ";
+    // Print the BI and BO fields
+    ss << crBit << ", " << opts;
 
     return ss.str();
 }