X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fx86%2Ffaults.cc;h=aa859052efbb75f648912f3fd5cd24acba6696d1;hb=502ad1e6757116867e0e0529c0c080320a2b440b;hp=20b5a931e8bb6774f72e0360bc7b001fadd16a17;hpb=13d64906c24349f48418e378050950b4e06daa36;p=gem5.git diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index 20b5a931e..aa859052e 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -40,26 +40,27 @@ * Authors: Gabe Black */ -#include "arch/x86/decoder.hh" +#include "arch/x86/generated/decoder.hh" #include "arch/x86/faults.hh" +#include "arch/x86/isa_traits.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "cpu/thread_context.hh" -#if !FULL_SYSTEM -#include "arch/x86/isa_traits.hh" -#include "mem/page_table.hh" -#include "sim/process.hh" -#else -#include "arch/x86/tlb.hh" -#endif +#include "debug/Faults.hh" +#include "sim/full_system.hh" namespace X86ISA { -#if FULL_SYSTEM - void X86FaultBase::invoke(ThreadContext * tc) + void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst) { - Addr pc = tc->readPC(); - DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe()); + if (!FullSystem) { + FaultBase::invoke(tc, inst); + return; + } + + PCState pcState = tc->pcState(); + Addr pc = pcState.pc(); + DPRINTF(Faults, "RIP %#x: vector %d: %s\n", + pc, vector, describe()); using namespace X86ISAInst::RomLabels; HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); MicroPC entry; @@ -81,13 +82,14 @@ namespace X86ISA panic("Legacy mode interrupts with error codes " "aren't implementde.\n"); } - // Software interrupts shouldn't have error codes. If one does, - // there would need to be microcode to set it up. + // Software interrupts shouldn't have error codes. If one + // does, there would need to be microcode to set it up. assert(!isSoft()); tc->setIntReg(INTREG_MICRO(15), errorCode); } - tc->setMicroPC(romMicroPC(entry)); - tc->setNextMicroPC(romMicroPC(entry) + 1); + pcState.upc(romMicroPC(entry)); + pcState.nupc(romMicroPC(entry) + 1); + tc->pcState(pcState); } std::string @@ -102,33 +104,60 @@ namespace X86ISA return ss.str(); } - void X86Trap::invoke(ThreadContext * tc) + void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst) { X86FaultBase::invoke(tc); - // This is the same as a fault, but it happens -after- the instruction. - tc->setPC(tc->readNextPC()); - tc->setNextPC(tc->readNextNPC()); - tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); + if (!FullSystem) + return; + + // This is the same as a fault, but it happens -after- the + // instruction. + PCState pc = tc->pcState(); + pc.uEnd(); } - void X86Abort::invoke(ThreadContext * tc) + void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst) { panic("Abort exception!"); } - void PageFault::invoke(ThreadContext * tc) + void + InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst) { - HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); - X86FaultBase::invoke(tc); - /* - * If something bad happens while trying to enter the page fault - * handler, I'm pretty sure that's a double fault and then all bets are - * off. That means it should be safe to update this state now. - */ - if (m5reg.mode == LongMode) { - tc->setMiscReg(MISCREG_CR2, addr); + if (FullSystem) { + X86Fault::invoke(tc, inst); + } else { + panic("Unrecognized/invalid instruction executed:\n %s", + inst->machInst); + } + } + + void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst) + { + if (FullSystem) { + HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); + X86FaultBase::invoke(tc); + /* + * If something bad happens while trying to enter the page fault + * handler, I'm pretty sure that's a double fault and then all + * bets are off. That means it should be safe to update this + * state now. + */ + if (m5reg.mode == LongMode) { + tc->setMiscReg(MISCREG_CR2, addr); + } else { + tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); + } } else { - tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); + PageFaultErrorCode code = errorCode; + const char *modeStr = ""; + if (code.fetch) + modeStr = "execute"; + else if (code.write) + modeStr = "write"; + else + modeStr = "read"; + panic("Tried to %s unmapped address %#x.\n", modeStr, addr); } } @@ -141,7 +170,7 @@ namespace X86ISA } void - InitInterrupt::invoke(ThreadContext *tc) + InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(Faults, "Init interrupt.\n"); // The otherwise unmodified integer registers should be set to 0. @@ -207,9 +236,8 @@ namespace X86ISA tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); - tc->setPC(0x000000000000fff0ULL + - tc->readMiscReg(MISCREG_CS_BASE)); - tc->setNextPC(tc->readPC() + sizeof(MachInst)); + PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE)); + tc->pcState(pc); tc->setMiscReg(MISCREG_TSG_BASE, 0); tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); @@ -240,15 +268,21 @@ namespace X86ISA tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL); tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL); + tc->setMiscReg(MISCREG_MXCSR, 0x1f80); + + // Flag all elements on the x87 stack as empty. + tc->setMiscReg(MISCREG_FTW, 0xFFFF); + // Update the handy M5 Reg. tc->setMiscReg(MISCREG_M5_REG, 0); MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt; - tc->setMicroPC(romMicroPC(entry)); - tc->setNextMicroPC(romMicroPC(entry) + 1); + pc.upc(romMicroPC(entry)); + pc.nupc(romMicroPC(entry) + 1); + tc->pcState(pc); } void - StartupInterrupt::invoke(ThreadContext *tc) + StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector); HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG); @@ -263,10 +297,7 @@ namespace X86ISA // This has the base value pre-added. tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff); - tc->setPC(tc->readMiscReg(MISCREG_CS_BASE)); - tc->setNextPC(tc->readPC() + sizeof(MachInst)); + tc->pcState(tc->readMiscReg(MISCREG_CS_BASE)); } - -#endif } // namespace X86ISA