X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fx86%2Finterrupts.cc;h=10387c07afd2b8947abc7915f8ca941c01672a81;hb=68127ca3da543db0c2f3d131d2b3f3525a35ec50;hp=6a9f07af2a5ee021a08ebc588c2f0e3e4c9758bf;hpb=1031b824b975cec999c37cabc8c05c485a4ae5ca;p=gem5.git diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 6a9f07af2..10387c07a 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012-2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2008 The Hewlett-Packard Development Company * All rights reserved. * @@ -37,6 +49,8 @@ * Authors: Gabe Black */ +#include + #include "arch/x86/regs/apic.hh" #include "arch/x86/interrupts.hh" #include "arch/x86/intmessage.hh" @@ -98,58 +112,34 @@ decodeAddr(Addr paddr) regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; break; case 0x100: - case 0x108: case 0x110: - case 0x118: case 0x120: - case 0x128: case 0x130: - case 0x138: case 0x140: - case 0x148: case 0x150: - case 0x158: case 0x160: - case 0x168: case 0x170: - case 0x178: - regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); + regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10); break; case 0x180: - case 0x188: case 0x190: - case 0x198: case 0x1A0: - case 0x1A8: case 0x1B0: - case 0x1B8: case 0x1C0: - case 0x1C8: case 0x1D0: - case 0x1D8: case 0x1E0: - case 0x1E8: case 0x1F0: - case 0x1F8: - regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); + regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10); break; case 0x200: - case 0x208: case 0x210: - case 0x218: case 0x220: - case 0x228: case 0x230: - case 0x238: case 0x240: - case 0x248: case 0x250: - case 0x258: case 0x260: - case 0x268: case 0x270: - case 0x278: - regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); + regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10); break; case 0x280: regNum = APIC_ERROR_STATUS; @@ -210,7 +200,7 @@ X86ISA::Interrupts::read(PacketPtr pkt) reg, offset, val); pkt->setData(((uint8_t *)&val) + (offset & mask(3))); pkt->makeAtomicResponse(); - return latency; + return pioDelay; } Tick @@ -228,7 +218,7 @@ X86ISA::Interrupts::write(PacketPtr pkt) reg, offset, gtoh(val)); setReg(reg, gtoh(val)); pkt->makeAtomicResponse(); - return latency; + return pioDelay; } void X86ISA::Interrupts::requestInterrupt(uint8_t vector, @@ -276,7 +266,7 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector, } } if (FullSystem) - cpu->wakeup(); + cpu->wakeup(0); } @@ -291,6 +281,7 @@ X86ISA::Interrupts::setCPU(BaseCPU * newCPU) cpu = newCPU; initialApicId = cpu->cpuId(); regs[APIC_ID] = (initialApicId << 24); + pioAddr = x86LocalAPICAddress(initialApicId, 0); } @@ -298,12 +289,16 @@ void X86ISA::Interrupts::init() { // - // The local apic must register its address ranges on both its pio port - // via the basicpiodevice(piodevice) init() function and its int port - // that it inherited from IntDev. Note IntDev is not a SimObject itself. + // The local apic must register its address ranges on both its pio + // port via the basicpiodevice(piodevice) init() function and its + // int port that it inherited from IntDevice. Note IntDevice is + // not a SimObject itself. // BasicPioDevice::init(); - IntDev::init(); + IntDevice::init(); + + // the slave port has a range so inform the connected master + intSlavePort.sendRangeChange(); } @@ -331,7 +326,7 @@ X86ISA::Interrupts::recvMessage(PacketPtr pkt) break; } pkt->makeAtomicResponse(); - return latency; + return pioDelay; } @@ -352,20 +347,7 @@ X86ISA::Interrupts::recvResponse(PacketPtr pkt) AddrRangeList -X86ISA::Interrupts::getAddrRanges() -{ - AddrRangeList ranges; - Range range = RangeEx(x86LocalAPICAddress(initialApicId, 0), - x86LocalAPICAddress(initialApicId, 0) + - PageBytes); - ranges.push_back(range); - pioAddr = range.start; - return ranges; -} - - -AddrRangeList -X86ISA::Interrupts::getIntAddrRange() +X86ISA::Interrupts::getIntAddrRange() const { AddrRangeList ranges; ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), @@ -395,9 +377,8 @@ X86ISA::Interrupts::readReg(ApicRegIndex reg) case APIC_CURRENT_COUNT: { if (apicTimerEvent.scheduled()) { - assert(clock); // Compute how many m5 ticks happen per count. - uint64_t ticksPerCount = clock * + uint64_t ticksPerCount = clockPeriod() * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); // Compute how many m5 ticks are left. uint64_t val = apicTimerEvent.when() - curTick(); @@ -486,8 +467,6 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) } low = val; InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; - // Record that an IPI is being sent. - low.deliveryStatus = 1; TriggerIntMessage message = 0; message.destination = high.destination; message.vector = low.vector; @@ -495,9 +474,6 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) message.destMode = low.destMode; message.level = low.level; message.trigger = low.trigger; - bool timing = sys->getMemoryMode() == Enums::timing; - // Be careful no updates of the delivery status bit get lost. - regs[APIC_INTERRUPT_COMMAND_LOW] = low; ApicList apics; int numContexts = sys->numContexts(); switch (low.destShorthand) { @@ -553,8 +529,13 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) } break; } - pendingIPIs += apics.size(); - intPort.sendMessage(apics, message, timing); + // Record that an IPI is being sent if one actually is. + if (apics.size()) { + low.deliveryStatus = 1; + pendingIPIs += apics.size(); + } + regs[APIC_INTERRUPT_COMMAND_LOW] = low; + intMasterPort.sendMessage(apics, message, sys->isTimingMode()); newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; } break; @@ -572,19 +553,21 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) break; case APIC_INITIAL_COUNT: { - assert(clock); newVal = bits(val, 31, 0); // Compute how many timer ticks we're being programmed for. uint64_t newCount = newVal * (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); // Schedule on the edge of the next tick plus the new count. - Tick offset = curTick() % clock; + Tick offset = curTick() % clockPeriod(); if (offset) { reschedule(apicTimerEvent, - curTick() + (newCount + 1) * clock - offset, true); + curTick() + (newCount + 1) * + clockPeriod() - offset, true); } else { - reschedule(apicTimerEvent, - curTick() + newCount * clock, true); + if (newCount) + reschedule(apicTimerEvent, + curTick() + newCount * + clockPeriod(), true); } } break; @@ -602,20 +585,18 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) } -X86ISA::Interrupts::Interrupts(Params * p) : - BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), - clock(0), - apicTimerEvent(this), - pendingSmi(false), smiVector(0), - pendingNmi(false), nmiVector(0), - pendingExtInt(false), extIntVector(0), - pendingInit(false), initVector(0), - pendingStartup(false), startupVector(0), - startedUp(false), pendingUnmaskableInt(false), - pendingIPIs(0), cpu(NULL), - intSlavePort(name() + ".int_slave", this, this, latency) +X86ISA::Interrupts::Interrupts(Params * p) + : BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency), + apicTimerEvent(this), + pendingSmi(false), smiVector(0), + pendingNmi(false), nmiVector(0), + pendingExtInt(false), extIntVector(0), + pendingInit(false), initVector(0), + pendingStartup(false), startupVector(0), + startedUp(false), pendingUnmaskableInt(false), + pendingIPIs(0), cpu(NULL), + intSlavePort(name() + ".int_slave", this, this) { - pioSize = PageBytes; memset(regs, 0, sizeof(regs)); //Set the local apic DFR to the flat model. regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); @@ -646,6 +627,14 @@ X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const return false; } +bool +X86ISA::Interrupts::checkInterruptsRaw() const +{ + return pendingUnmaskableInt || pendingExtInt || + (IRRV > ISRV && bits(IRRV, 7, 4) > + bits(regs[APIC_TASK_PRIORITY], 7, 4)); +} + Fault X86ISA::Interrupts::getInterrupt(ThreadContext *tc) { @@ -655,16 +644,16 @@ X86ISA::Interrupts::getInterrupt(ThreadContext *tc) if (pendingUnmaskableInt) { if (pendingSmi) { DPRINTF(LocalApic, "Generated SMI fault object.\n"); - return new SystemManagementInterrupt(); + return std::make_shared(); } else if (pendingNmi) { DPRINTF(LocalApic, "Generated NMI fault object.\n"); - return new NonMaskableInterrupt(nmiVector); + return std::make_shared(nmiVector); } else if (pendingInit) { DPRINTF(LocalApic, "Generated INIT fault object.\n"); - return new InitInterrupt(initVector); + return std::make_shared(initVector); } else if (pendingStartup) { DPRINTF(LocalApic, "Generating SIPI fault object.\n"); - return new StartupInterrupt(startupVector); + return std::make_shared(startupVector); } else { panic("pendingUnmaskableInt set, but no unmaskable " "ints were pending.\n"); @@ -672,11 +661,11 @@ X86ISA::Interrupts::getInterrupt(ThreadContext *tc) } } else if (pendingExtInt) { DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); - return new ExternalInterrupt(extIntVector); + return std::make_shared(extIntVector); } else { DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); // The only thing left are fixed and lowest priority interrupts. - return new ExternalInterrupt(IRRV); + return std::make_shared(IRRV); } } @@ -716,10 +705,9 @@ X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) } void -X86ISA::Interrupts::serialize(std::ostream &os) +X86ISA::Interrupts::serialize(CheckpointOut &cp) const { SERIALIZE_ARRAY(regs, NUM_APIC_REGS); - SERIALIZE_SCALAR(clock); SERIALIZE_SCALAR(pendingSmi); SERIALIZE_SCALAR(smiVector); SERIALIZE_SCALAR(pendingNmi); @@ -742,10 +730,9 @@ X86ISA::Interrupts::serialize(std::ostream &os) } void -X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) +X86ISA::Interrupts::unserialize(CheckpointIn &cp) { UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); - UNSERIALIZE_SCALAR(clock); UNSERIALIZE_SCALAR(pendingSmi); UNSERIALIZE_SCALAR(smiVector); UNSERIALIZE_SCALAR(pendingNmi);