X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fx86%2Fisa%2Fdecoder%2Ftwo_byte_opcodes.isa;h=6b24b38262ccad32452c8f35e2a95836ac4872f7;hb=ae4ee21ecd65107a96fe22692ed5d2ea39b873b5;hp=717a8f26fa22c79d58e08b222ad60a980cdd2a21;hpb=557bc8064752ac66c099542956af63670a666de5;p=gem5.git diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 717a8f26f..6b24b3826 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -1,4 +1,32 @@ -// Copyright (c) 2007 The Hewlett-Packard Development Company +// Copyright (c) 2008 The Regents of The University of Michigan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +// Copyright (c) 2007-2008 The Hewlett-Packard Development Company // All rights reserved. // // Redistribution and use of this software in source and binary forms, @@ -65,8 +93,8 @@ 0x00: decode MODRM_REG { 0x0: sldt_Mw_or_Rv(); 0x1: str_Mw_or_Rv(); - 0x2: lldt_Mw_or_Rv(); - 0x3: ltr_Mw_or_Rv(); + 0x2: Inst::LLDT(Ew); + 0x3: Inst::LTR(Ew); 0x4: verr_Mw_or_Rv(); 0x5: verw_Mw_or_Rv(); //0x6: jmpe_Ev(); // IA-64 @@ -97,10 +125,10 @@ 0x6: skinit(); 0x7: invlpga(); } - 0x4: smsw_Rv(); - 0x6: lmsw_Rv(); + 0x4: Inst::SMSW(Rv); + 0x6: Inst::LMSW(Rv); 0x7: decode MODRM_RM { - 0x0: swapgs(); + 0x0: Inst::SWAPGS(); 0x1: rdtscp(); default: Inst::UD2(); } @@ -127,25 +155,125 @@ default: Inst::LIDT(M); } } - 0x4: smsw_Mw(); - 0x6: lmsw_Mw(); - 0x7: invlpg_M(); + 0x4: Inst::SMSW(Mw); + 0x6: Inst::LMSW(Mw); + 0x7: Inst::INVLPG(M); default: Inst::UD2(); } } 0x02: lar_Gv_Ew(); 0x03: lsl_Gv_Ew(); - //sandpile.org doesn't seem to know what this is... ? - 0x04: loadall_or_reset_or_hang(); + // sandpile.org doesn't seem to know what this is...? We'll + // use it for pseudo instructions. We've got 16 bits of space + // to play with so there can be quite a few pseudo + // instructions. + //0x04: loadall_or_reset_or_hang(); + 0x4: decode IMMEDIATE { + format BasicOperate { +#if FULL_SYSTEM + 0x00: m5arm({{ + PseudoInst::arm(xc->tcBase()); + }}, IsNonSpeculative); + 0x01: m5quiesce({{ + PseudoInst::quiesce(xc->tcBase()); + }}, IsNonSpeculative); + 0x02: m5quiesceNs({{ + PseudoInst::quiesceNs(xc->tcBase(), Rdi); + }}, IsNonSpeculative); + 0x03: m5quiesceCycle({{ + PseudoInst::quiesceCycles(xc->tcBase(), Rdi); + }}, IsNonSpeculative); + 0x04: m5quiesceTime({{ + Rax = PseudoInst::quiesceTime(xc->tcBase()); + }}, IsNonSpeculative); +#endif + 0x07: m5rpns({{ + Rax = PseudoInst::rpns(xc->tcBase()); + }}, IsNonSpeculative); + 0x21: m5exit({{ + PseudoInst::m5exit(xc->tcBase(), Rdi); + }}, IsNonSpeculative); +#if FULL_SYSTEM + 0x30: m5initparam({{ + Rax = xc->tcBase()->getCpuPtr()-> + system->init_param; + }}, IsNonSpeculative); + 0x31: m5loadsymbol({{ + PseudoInst::loadsymbol(xc->tcBase()); + }}, IsNonSpeculative); +#endif + 0x40: m5resetstats({{ + PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); + 0x41: m5dumpstats({{ + PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); + 0x42: m5dumpresetstats({{ + PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); + 0x43: m5checkpoint({{ + PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); +#if FULL_SYSTEM + 0x50: m5readfile({{ + Rax = PseudoInst::readfile( + xc->tcBase(), Rdi, Rsi, Rdx); + }}, IsNonSpeculative); +#endif + 0x51: m5debugbreak({{ + PseudoInst::debugbreak(xc->tcBase()); + }}, IsNonSpeculative); + 0x52: m5switchcpu({{ + PseudoInst::switchcpu(xc->tcBase()); + }}, IsNonSpeculative); +#if FULL_SYSTEM + 0x53: m5addsymbol({{ + PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); +#endif + 0x54: m5panic({{ + panic("M5 panic instruction called at pc=%#x.\n", + xc->readPC()); + }}, IsNonSpeculative); + 0x55: m5reserved1({{ + warn("M5 reserved opcode 1 ignored.\n"); + }}, IsNonSpeculative); + 0x56: m5reserved2({{ + warn("M5 reserved opcode 2 ignored.\n"); + }}, IsNonSpeculative); + 0x57: m5reserved3({{ + warn("M5 reserved opcode 3 ignored.\n"); + }}, IsNonSpeculative); + 0x58: m5reserved4({{ + warn("M5 reserved opcode 4 ignored.\n"); + }}, IsNonSpeculative); + 0x59: m5reserved5({{ + warn("M5 reserved opcode 5 ignored.\n"); + }}, IsNonSpeculative); + default: Inst::UD2(); + } + } #if FULL_SYSTEM - 0x05: syscall(); + 0x05: decode MODE_MODE { + 0x0: decode MODE_SUBMODE { + 0x0: Inst::SYSCALL_64(); + 0x1: Inst::SYSCALL_COMPAT(); + } + 0x1: Inst::SYSCALL_LEGACY(); + } #else - 0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall); + 0x05: SyscallInst::syscall('xc->syscall(Rax)', IsSyscall); #endif - 0x06: clts(); - //sandpile.org says (AMD) after sysret, so I might want to check - //if that means amd64 or AMD machines - 0x07: loadall_or_sysret(); + 0x06: Inst::CLTS(); + 0x07: decode MODE_SUBMODE { + 0x0: decode OPSIZE { + // Return to 64 bit mode. + 0x8: Inst::SYSRET_TO_64(); + // Return to compatibility mode. + default: Inst::SYSRET_TO_COMPAT(); + } + default: Inst::SYSRET_NON_64(); + } } 0x01: decode OPCODE_OP_BOTTOM3 { 0x0: invd(); @@ -153,9 +281,9 @@ 0x2: Inst::UD2(); 0x3: Inst::UD2(); 0x4: Inst::UD2(); - 0x5: threednow(); - 0x6: threednow(); - 0x7: threednow(); + 0x5: Inst::PREFETCH(Mb); + 0x6: FailUnimpl::femms(); + 0x7: FailUnimpl::threednow(); } 0x02: decode LEGACY_DECODEVAL { // no prefix @@ -204,22 +332,29 @@ default: Inst::UD2(); } 0x03: decode OPCODE_OP_BOTTOM3 { - 0x0: group17(); - 0x1: group17(); - 0x2: group17(); - 0x3: group17(); - 0x4: group17(); - 0x5: group17(); - 0x6: group17(); - 0x7: group17(); + //group17(); + 0x0: decode MODRM_REG { + 0x0: prefetch_nta(); + 0x1: Inst::PREFETCH_T0(Mb); + 0x2: prefetch_t1(); + 0x3: prefetch_t2(); + default: Inst::HINT_NOP(); + } + 0x1: Inst::HINT_NOP(); + 0x2: Inst::HINT_NOP(); + 0x3: Inst::HINT_NOP(); + 0x4: Inst::HINT_NOP(); + 0x5: Inst::HINT_NOP(); + 0x6: Inst::HINT_NOP(); + 0x7: Inst::HINT_NOP(); } 0x04: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_Rd_Cd(); - 0x1: mov_Rd_Dd(); + 0x0: Inst::MOV(Rd,Cd); + 0x1: Inst::MOV(Rd,Dd); 0x2: Inst::MOV(Cd,Rd); - 0x3: mov_Dd_Rd(); + 0x3: Inst::MOV(Dd,Rd); 0x4: mov_Rd_Td(); 0x6: mov_Td_Rd(); default: Inst::UD2(); @@ -282,10 +417,14 @@ } 0x06: decode OPCODE_OP_BOTTOM3 { 0x0: Inst::WRMSR(); - 0x1: rdtsc(); + 0x1: Inst::RDTSC(); 0x2: Inst::RDMSR(); 0x3: rdpmc(); +#if FULL_SYSTEM 0x4: sysenter(); +#else + 0x4: SyscallInst::sysenter('xc->syscall(Rax)', IsSyscall); +#endif 0x5: sysexit(); 0x6: Inst::UD2(); 0x7: getsec(); @@ -412,7 +551,7 @@ 0x0C: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { - 0x0: punpcklbw_Pq_Qd(); + 0x0: Inst::PUNPCKLBW(Pq,Qd); 0x1: punpcklwd_Pq_Qd(); 0x2: punpckldq_Pq_Qd(); 0x3: packsswb_Pq_Qq(); @@ -423,7 +562,7 @@ } // operand size (0x66) 0x1: decode OPCODE_OP_BOTTOM3 { - 0x0: punpcklbw_Vo_Wq(); + 0x0: Inst::PUNPCKLBW(Vo,Wq); 0x1: punpcklwd_Vo_Wq(); 0x2: punpckldq_Vo_Wq(); 0x3: packsswb_Vo_Wo(); @@ -441,8 +580,8 @@ 0x1: punpckhwd_Pq_Qq(); 0x2: punpckhdq_Pq_Qq(); 0x3: packssdw_Pq_Qq(); - 0x6: movd_Pq_Ed(); - 0x7: movq_Pq_Qq(); + 0x6: Inst::MOVD(Pq,Edp); + 0x7: Inst::MOVQ(Pq,Qq); default: Inst::UD2(); } // repe (0xF3) @@ -601,13 +740,13 @@ 0x0: decode OPCODE_OP_BOTTOM3 { 0x0: vmread_Ed_or_Eq_Gd_or_Gq(); 0x1: vmwrite_Gd_or_Gq_Ed_or_Eq(); - 0x6: mov_Ed_Pd(); - 0x7: mov_Qq_Pq(); + 0x6: Inst::MOVD(Edp,Pdp); + 0x7: Inst::MOVQ(Qq,Pq); default: Inst::UD2(); } // repe (0xF3) 0x4: decode OPCODE_OP_BOTTOM3 { - 0x6: movq_Vo_Mq_or_Vq_Vq(); + 0x6: Inst::MOVQ(Vq,Wq); 0x7: movdqu_Wo_Vo(); default: Inst::UD2(); } @@ -672,10 +811,17 @@ 0x14: decode OPCODE_OP_BOTTOM3 { 0x0: push_fs(); 0x1: pop_fs(); - 0x2: Inst::CPUID(rAd); + 0x2: CPUIDInst::CPUID({{ + CpuidResult result; + success = doCpuid(xc->tcBase(), bits(Rax, 31, 0), result); + Rax = result.rax; + Rbx = result.rbx; + Rcx = result.rcx; + Rdx = result.rdx; + }}); 0x3: Inst::BT(Ev,Gv); - 0x4: shld_Ev_Gv_Ib(); - 0x5: shld_Ev_Gv_rCl(); + 0x4: Inst::SHLD(Ev,Gv,Ib); + 0x5: Inst::SHLD(Ev,Gv); 0x6: xbts_and_cmpxchg(); 0x7: ibts_and_cmpxchg(); } @@ -684,20 +830,28 @@ 0x1: pop_gs(); 0x2: rsm_smm(); 0x3: Inst::BTS(Ev,Gv); - 0x4: shrd_Ev_Gv_Ib(); - 0x5: shrd_Ev_Gv_rCl(); + 0x4: Inst::SHRD(Ev,Gv,Ib); + 0x5: Inst::SHRD(Ev,Gv); //0x6: group16(); - 0x6: decode MODRM_MOD { - 0x3: decode MODRM_REG { - 0x5: lfence(); - 0x6: mfence(); - 0x7: sfence(); + 0x6: decode MODRM_REG { + 0x0: fxsave(); + 0x1: fxrstor(); + 0x2: ldmxcsr(); + 0x3: stmxcsr(); + 0x4: Inst::UD2(); + 0x5: decode MODRM_MOD { + 0x3: BasicOperate::LFENCE( + {{/*Nothing*/}}, IsReadBarrier); default: Inst::UD2(); } - default: decode MODRM_REG { - 0x0: fxsave(); - 0x1: fxrstor(); - 0x7: clflush(); + 0x6: decode MODRM_MOD { + 0x3: BasicOperate::MFENCE( + {{/*Nothing*/}}, IsMemBarrier); + default: Inst::UD2(); + } + 0x7: decode MODRM_MOD { + 0x3: BasicOperate::SFENCE( + {{/*Nothing*/}}, IsWriteBarrier); default: Inst::UD2(); } } @@ -731,8 +885,8 @@ } 0x3: BTC(Ev,Gv); } - 0x4: bsf_Gv_Ev(); - 0x5: bsr_Gv_Ev(); + 0x4: Inst::BSF(Gv,Ev); + 0x5: Inst::BSR(Gv,Ev); //The size of the second operand in these instructions should //really be "b" or "w", but it's set to v in order to have a //consistent register size. This shouldn't affect behavior. @@ -740,11 +894,12 @@ 0x7: Inst::MOVSX_W(Gv,Ev); } 0x18: decode OPCODE_OP_BOTTOM3 { - 0x0: xadd_Eb_Gb(); - 0x1: xadd_Ev_Gv(); + 0x0: Inst::XADD(Eb,Gb); + 0x1: Inst::XADD(Ev,Gv); //0x7: group9(); 0x7: decode MODRM_REG { - 0x1: cmpxchg_Mq(); + //Also CMPXCHG16B + 0x1: Inst::CMPXCHG8B(Mdp); 0x6: decode LEGACY_OP { 0x1: vmclear_Mq(); default: decode LEGACY_REP { @@ -785,7 +940,11 @@ default: Inst::UD2(); } } - 0x19: bswap_B(); + 0x19: decode OPSIZE { + 4: Inst::BSWAP_D(Bd); + 8: Inst::BSWAP_Q(Bq); + default: Inst::UD2(); + } 0x1A: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { @@ -810,10 +969,7 @@ 0x3: psrlq_Vo_Wo(); 0x4: paddq_Vo_Wo(); 0x5: pmullw_Vo_Wo(); - 0x6: decode MODRM_MOD { - 0x3: movq_Vq_Vq(); - default: movq_Mq_Vq(); - } + 0x6: Inst::MOVQ(Wq,Vq); 0x7: pmovmskb_Gd_VRo(); } // repne (0xF2) @@ -909,7 +1065,7 @@ } default: Inst::UD2(); } - 0x1E: decode OPCODE_OP_BOTTOM3 { + 0x1E: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { 0x1: psllw_Pq_Qq();