X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fx86%2Ftlb.hh;h=53f61dcbc2023dab84a93f8d85b84d93e05d22b2;hb=68127ca3da543db0c2f3d131d2b3f3525a35ec50;hp=f67a93d8d4523991eaebd8d5f5893566b14e0b3d;hpb=7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60;p=gem5.git diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index f67a93d8d..53f61dcbc 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -2,43 +2,25 @@ * Copyright (c) 2007 The Hewlett-Packard Development Company * All rights reserved. * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. + * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -59,17 +41,16 @@ #define __ARCH_X86_TLB_HH__ #include -#include #include +#include +#include "arch/generic/tlb.hh" +#include "arch/x86/regs/segment.hh" #include "arch/x86/pagetable.hh" -#include "arch/x86/segmentregs.hh" -#include "config/full_system.hh" +#include "base/trie.hh" #include "mem/mem_object.hh" #include "mem/request.hh" #include "params/X86TLB.hh" -#include "sim/faults.hh" -#include "sim/tlb.hh" #include "sim/sim_object.hh" class ThreadContext; @@ -79,8 +60,6 @@ namespace X86ISA { class Walker; - static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; - class TLB : public BaseTLB { protected: @@ -95,7 +74,7 @@ namespace X86ISA typedef X86TLBParams Params; TLB(const Params *p); - void dumpAll(); + void takeOverFrom(BaseTLB *otlb) override {} TlbEntry *lookup(Addr va, bool update_lru = true); @@ -105,49 +84,84 @@ namespace X86ISA EntryList::iterator lookupIt(Addr va, bool update_lru = true); -#if FULL_SYSTEM - protected: - Walker * walker; -#endif public: - void invalidateAll(); + Walker *getWalker(); - void invalidateNonGlobal(); + void flushAll() override; - void demapPage(Addr va, uint64_t asn); + void flushNonGlobal(); + + void demapPage(Addr va, uint64_t asn) override; protected: - int size; + uint32_t size; - TlbEntry * tlb; + std::vector tlb; EntryList freeList; - EntryList entryList; + + TlbEntryTrie trie; + uint64_t lruSeq; + + Fault translateInt(RequestPtr req, ThreadContext *tc); Fault translate(RequestPtr req, ThreadContext *tc, - Translation *translation, bool write, bool execute, + Translation *translation, Mode mode, bool &delayedResponse, bool timing); public: - Fault translateAtomic(RequestPtr req, ThreadContext *tc, - bool write = false, bool execute = false); - void translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, - bool write = false, bool execute = false); + void evictLRU(); + + uint64_t + nextSeq() + { + return ++lruSeq; + } -#if FULL_SYSTEM - Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); - Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); -#endif + Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode); + /** Stub function for compilation support of CheckerCPU. x86 ISA does + * not support Checker model at the moment + */ + Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + + /** + * Do post-translation physical address finalization. + * + * Some addresses, for example requests going to the APIC, + * need post-translation updates. Such physical addresses are + * remapped into a "magic" part of the physical address space + * by this method. + * + * @param req Request to updated in-place. + * @param tc Thread context that created the request. + * @param mode Request type (read/write/execute). + * @return A fault on failure, NoFault otherwise. + */ + Fault finalizePhysical(RequestPtr req, ThreadContext *tc, + Mode mode) const; TlbEntry * insert(Addr vpn, TlbEntry &entry); // Checkpointing - virtual void serialize(std::ostream &os); - virtual void unserialize(Checkpoint *cp, const std::string §ion); + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; + + /** + * Get the table walker master port. This is used for + * migrating port connections during a CPU takeOverFrom() + * call. For architectures that do not have a table walker, + * NULL is returned, hence the use of a pointer rather than a + * reference. For X86 this method will always return a valid + * port pointer. + * + * @return A pointer to the walker master port + */ + BaseMasterPort *getMasterPort() override; }; }