X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fx86%2Futility.cc;h=cf30723487bb03eefb3b49f047e405b02b054ae2;hb=68127ca3da543db0c2f3d131d2b3f3525a35ec50;hp=e1be61180935ae7b749283b2994be62db6db48ca;hpb=608641e23c7f2288810c3f23a1a63790b664f2ab;p=gem5.git

diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index e1be61180..cf3072348 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -183,7 +183,7 @@ void initCPU(ThreadContext *tc, int cpuId)
     tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
 
     Interrupts * interrupts = dynamic_cast<Interrupts *>(
-            tc->getCpuPtr()->getInterruptController());
+            tc->getCpuPtr()->getInterruptController(0));
     assert(interrupts);
 
     interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
@@ -217,11 +217,9 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
     // need to be considered while copying state. That will likely not be
     // true in the future.
     for (int i = 0; i < NUM_MISCREGS; ++i) {
-        if ( ( i != MISCREG_CR1 &&
-             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
-             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
+        if (!isValidMiscReg(i))
              continue;
-        }
+
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
     }
 
@@ -245,10 +243,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     //copy condition-code regs
     for (int i = 0; i < NumCCRegs; ++i)
          dest->setCCRegFlat(i, src->readCCRegFlat(i));
-
-    // copy vector regs when added to the architecture
-    assert(NumVectorRegs == 0);
-
     copyMiscRegs(src, dest);
     dest->pcState(src->pcState());
 }