X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Farch%2Fx86%2Futility.hh;h=f3b0d3fa11f6a3d11ccc9356f8bd0f296fbe3378;hb=52540b1b785aac9b307dfcc976527d94899deb94;hp=d89e223de5c1ca7b8212a97880c2b2eb8d94cd25;hpb=c6e1dc61c23dc1f5300610ce8348f9a0e9c128cc;p=gem5.git diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index d89e223de..f3b0d3fa1 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -2,43 +2,25 @@ * Copyright (c) 2007 The Hewlett-Packard Development Company * All rights reserved. * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. + * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -58,68 +40,40 @@ #ifndef __ARCH_X86_UTILITY_HH__ #define __ARCH_X86_UTILITY_HH__ +#include "arch/x86/regs/misc.hh" #include "arch/x86/types.hh" #include "base/hashmap.hh" #include "base/misc.hh" +#include "base/types.hh" +#include "cpu/static_inst.hh" #include "cpu/thread_context.hh" -#include "sim/host.hh" +#include "sim/full_system.hh" class ThreadContext; -namespace __hash_namespace { - template<> - struct hash { - size_t operator()(const X86ISA::ExtMachInst &emi) const { - //Because these are all the same, return 0 - return 0; - }; - }; -} - namespace X86ISA { - static inline bool - inUserMode(ThreadContext *tc) - { - return false; - } - - inline bool isCallerSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCalleeSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCallerSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - inline bool isCalleeSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - // Instruction address compression hooks - inline Addr realPCToFetchPC(const Addr &addr) + inline PCState + buildRetPC(const PCState &curPC, const PCState &callPC) { - return addr; + PCState retPC = callPC; + retPC.uEnd(); + return retPC; } - inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } + uint64_t + getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - inline size_t fetchInstSize() + static inline bool + inUserMode(ThreadContext *tc) { - return sizeof(MachInst); + if (!FullSystem) { + return true; + } else { + HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); + return m5reg.cpl == 3; + } } /** @@ -129,15 +83,28 @@ namespace X86ISA template void zeroRegisters(TC *tc); - inline void initCPU(ThreadContext *tc, int cpuId) + void initCPU(ThreadContext *tc, int cpuId); + + void startupCPU(ThreadContext *tc, int cpuId); + + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + + void skipFunction(ThreadContext *tc); + + inline void + advancePC(PCState &pc, const StaticInstPtr inst) { - panic("initCPU not implemented!\n"); + inst->advancePC(pc); } - inline void startupCPU(ThreadContext *tc, int cpuId) + inline uint64_t + getExecutingAsid(ThreadContext *tc) { - tc->activate(0); + return 0; } -}; + +} #endif // __ARCH_X86_UTILITY_HH__