X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbroadcom%2Fqpu%2Fqpu_pack.c;h=6942342740c323a5020d31a0e3005b68dd543111;hb=6e68f743953d79f2beb2ac1fc34331f016d1b7c7;hp=ffabc9a969d1a9d82b406436c0b7bb97590b2faa;hpb=22a02f3e344d6bc47e3e30949a36d00a9eae84a9;p=mesa.git diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c index ffabc9a969d..6942342740c 100644 --- a/src/broadcom/qpu/qpu_pack.c +++ b/src/broadcom/qpu/qpu_pack.c @@ -492,7 +492,8 @@ static const struct opcode_desc add_ops[] = { { 186, 186, 1 << 1, ANYMUX, V3D_QPU_A_NEG }, { 186, 186, 1 << 2, ANYMUX, V3D_QPU_A_FLAPUSH }, { 186, 186, 1 << 3, ANYMUX, V3D_QPU_A_FLBPUSH }, - { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLBPOP }, + { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLPOP }, + { 186, 186, 1 << 5, ANYMUX, V3D_QPU_A_RECIP }, { 186, 186, 1 << 6, ANYMUX, V3D_QPU_A_SETMSF }, { 186, 186, 1 << 7, ANYMUX, V3D_QPU_A_SETREVF }, { 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP, 0 }, @@ -511,15 +512,26 @@ static const struct opcode_desc add_ops[] = { { 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF }, { 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF }, - { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT }, + { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT, 33 }, + { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_IID, 40 }, + { 187, 187, 1 << 2, 1 << 3, V3D_QPU_A_SAMPID, 40 }, + { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID, 40 }, { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT }, { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT }, { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP, 33 }, { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_IN, 40 }, + { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_OUT, 40 }, { 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_IN, 40 }, + { 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_OUT, 40 }, { 188, 188, 1 << 2, ANYMUX, V3D_QPU_A_LDVPMP, 40 }, + { 188, 188, 1 << 3, ANYMUX, V3D_QPU_A_RSQRT, 41 }, + { 188, 188, 1 << 4, ANYMUX, V3D_QPU_A_EXP, 41 }, + { 188, 188, 1 << 5, ANYMUX, V3D_QPU_A_LOG, 41 }, + { 188, 188, 1 << 6, ANYMUX, V3D_QPU_A_SIN, 41 }, + { 188, 188, 1 << 7, ANYMUX, V3D_QPU_A_RSQRT2, 41 }, { 189, 189, ANYMUX, ANYMUX, V3D_QPU_A_LDVPMG_IN, 40 }, + { 189, 189, ANYMUX, ANYMUX, V3D_QPU_A_LDVPMG_OUT, 40 }, /* FIXME: MORE COMPLICATED */ /* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */ @@ -767,7 +779,11 @@ v3d_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst, case V3D_QPU_A_FMIN: case V3D_QPU_A_FMAX: case V3D_QPU_A_FCMP: - instr->alu.add.output_pack = (op >> 4) & 0x3; + case V3D_QPU_A_VFPACK: + if (instr->alu.add.op != V3D_QPU_A_VFPACK) + instr->alu.add.output_pack = (op >> 4) & 0x3; + else + instr->alu.add.output_pack = V3D_QPU_PACK_NONE; if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3, &instr->alu.add.a_unpack)) { @@ -1033,6 +1049,32 @@ v3d_qpu_add_pack(const struct v3d_device_info *devinfo, opcode |= a_unpack << 2; opcode |= b_unpack << 0; + + break; + } + + case V3D_QPU_A_VFPACK: { + uint32_t a_unpack; + uint32_t b_unpack; + + if (instr->alu.add.a_unpack == V3D_QPU_UNPACK_ABS || + instr->alu.add.b_unpack == V3D_QPU_UNPACK_ABS) { + return false; + } + + if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack, + &a_unpack)) { + return false; + } + + if (!v3d_qpu_float32_unpack_pack(instr->alu.add.b_unpack, + &b_unpack)) { + return false; + } + + opcode = (opcode & ~(1 << 2)) | (a_unpack << 2); + opcode = (opcode & ~(1 << 0)) | (b_unpack << 0); + break; } @@ -1056,7 +1098,7 @@ v3d_qpu_add_pack(const struct v3d_device_info *devinfo, } if (packed == 0) return false; - opcode |= packed << 2; + opcode = (opcode & ~(1 << 2)) | packed << 2; break; }