X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fbase.py;h=6c455fa8faeb1a798d6ecedde0bd3b44dd3d825f;hb=893accd585e3b7fd918bc166d107b1df4d79813c;hp=642557d0ab62fb098c60be13db27ff9562cdf95a;hpb=b098b124a061a0345f91252ab96ca107a06be80f;p=pinmux.git

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 642557d..6c455fa 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -45,12 +45,16 @@ class PBase(object):
                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
                 offs)
 
-    def axi_slave_name(self, name, ifacenum):
+    def axi_master_name(self, name, ifacenum):
         name = name.upper()
-        return "{0}{1}_slave_num".format(name, ifacenum)
+        return "{0}{1}_laster_num".format(name, ifacenum)
 
-    def axi_slave_idx(self, idx, name, ifacenum):
-        name = self.axi_slave_name(name, ifacenum)
+    def axi_slave_name(self, name, ifacenum, typ=''):
+        name = name.upper()
+        return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
+
+    def axi_slave_idx(self, idx, name, ifacenum, typ):
+        name = self.axi_slave_name(name, ifacenum, typ)
         return ("typedef {0} {1};".format(idx, name), 1)
 
     def axi_addr_map(self, name, ifacenum):
@@ -200,6 +204,21 @@ mkplic_rule = """\
 """
 
 
+axi_fastslave_declarations = """\
+{0}
+typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
+typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )      Sdram_cfg_slave_num;
+typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )      BootRom_slave_num   ;
+typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )      Debug_slave_num ;
+typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )      TCM_slave_num;
+typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )  Dma_slave_num;
+typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
+typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )       VME_slave_num;
+typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )              FlexBus_slave_num;
+typedef TAdd#(FlexBus_slave_num,1)                       Num_Slaves;
+
+"""
+
 axi_slave_declarations = """\
 typedef  0  SlowMaster;
 {0}
@@ -262,10 +281,10 @@ class PeripheralIface(object):
             return ('', 0)
         return self.slow.axi_reg_def(start, self.ifacename, count)
 
-    def axi_slave_idx(self, start, count):
+    def axi_slave_idx(self, start, count, typ):
         if not self.slow:
             return ('', 0)
-        return self.slow.axi_slave_idx(start, self.ifacename, count)
+        return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 
     def axi_addr_map(self, count):
         if not self.slow:
@@ -333,20 +352,27 @@ class PeripheralInterfaces(object):
                 start += offs
         return '\n'.join(list(filter(None, ret)))
 
-    def axi_slave_idx(self, *args):
+    def _axi_num_idx(self, start, template, typ, idxtype, *args):
         ret = []
-        start = 0
         for (name, count) in self.ifacecount:
             for i in range(count):
                 if self.is_on_fastbus(name, i):
                     continue
-                (rdef, offs) = self.data[name].axi_slave_idx(start, i)
+                (rdef, offs) = self.data[name].axi_slave_idx(start, i, idxtype)
                 #print ("ifc", name, rdef, offs)
                 ret.append(rdef)
                 start += offs
-        ret.append("typedef %d LastGen_slave_num;" % (start - 1))
+        ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
         decls = '\n'.join(list(filter(None, ret)))
-        return axi_slave_declarations.format(decls)
+        return template.format(decls)
+
+    def axi_slave_idx(self, *args):
+        return self._axi_num_idx(0, axi_slave_declarations, 'slave',
+                                 '', *args)
+
+    def axi_fastslave_idx(self, *args):
+        return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
+                                 'fast', *args)
 
     def axi_addr_map(self, *args):
         ret = []