X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen.py;h=d424778ee096163fa0a27ccc18090567d4518c69;hb=180f70b03d99ed3fe2838dda1dc34072f626a13f;hp=c31e081cedded31573d622e463e8e418d41f9e50;hpb=5455ea2d9ad702d3b8d0c8e7e990cb7112d9780e;p=pinmux.git

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index c31e081..d424778 100644
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -63,7 +63,10 @@ class PBase(object):
                         ps_ = ps + '_out'
                     else:
                         ps_ = ps
-                    n_ = "{0}{1}".format(n, count)
+                    if not n.startswith('gpio'): # XXX EURGH! horrible hack
+                      n_ = "{0}{1}".format(n, count)
+                    else:
+                      n_ = n
                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
                 fname = None
                 if p.get('outen'):
@@ -84,7 +87,8 @@ class PBase(object):
                     ret.append(
                         "    rule con_%s%d_%s_in;" %
                         (name, count, pname))
-                    ret.append("      {1}.{2}({0});".format(ps_, n, fname))
+                    n_ = "{0}{1}".format(n, count)
+                    ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
                     ret.append("    endrule")
         return '\n'.join(ret)
 
@@ -217,8 +221,8 @@ class twi(PBase):
                 'scl': 'out.scl_in'}.get(pname, '')
 
     def pinname_outen(self, pname):
-        return {'sda': 'out.sda_outen',
-                'scl': 'out.scl_outen'}.get(pname, '')
+        return {'sda': 'out.sda_out_en',
+                'scl': 'out.scl_out_en'}.get(pname, '')
 
     def pinname_tweak(self, pname, typ, txt):
         if typ == 'outen':
@@ -293,7 +297,7 @@ class pwm(PBase):
         return "        import pwm::*;"
 
     def slowifdecl(self):
-        return "        interface PWMIO pwm{0}_o;"
+        return "        interface PWMIO pwm{0};"
 
     def num_axi_regs32(self):
         return 4