X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcompiler%2Fnir%2Fnir.h;h=02d0a6000dae0807e584af69c27e88c9ad848fcc;hb=5746af444606b77e30309d5b85bc116d64df2cf4;hp=c90b025f0a89021fc148f3707c413267b441003b;hpb=fb2fe802f638d7a70f0d00ec1d496f317d241765;p=mesa.git diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index c90b025f0a8..02d0a6000da 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -3941,7 +3941,7 @@ void nir_assign_var_locations(struct exec_list *var_list, unsigned *size, /* Some helpers to do very simple linking */ bool nir_remove_unused_varyings(nir_shader *producer, nir_shader *consumer); -bool nir_remove_unused_io_vars(nir_shader *shader, struct exec_list *var_list, +bool nir_remove_unused_io_vars(nir_shader *shader, nir_variable_mode mode, uint64_t *used_by_other_stage, uint64_t *used_by_other_stage_patches); void nir_compact_varyings(nir_shader *producer, nir_shader *consumer, @@ -4017,6 +4017,12 @@ typedef enum { */ nir_address_format_32bit_index_offset, + /** + * An address format which is comprised of a vec3 where the first two + * components specify the buffer and the third is an offset. + */ + nir_address_format_vec2_index_32bit_offset, + /** * An address format which is a simple 32-bit offset. */ @@ -4036,12 +4042,13 @@ static inline unsigned nir_address_format_bit_size(nir_address_format addr_format) { switch (addr_format) { - case nir_address_format_32bit_global: return 32; - case nir_address_format_64bit_global: return 64; - case nir_address_format_64bit_bounded_global: return 32; - case nir_address_format_32bit_index_offset: return 32; - case nir_address_format_32bit_offset: return 32; - case nir_address_format_logical: return 32; + case nir_address_format_32bit_global: return 32; + case nir_address_format_64bit_global: return 64; + case nir_address_format_64bit_bounded_global: return 32; + case nir_address_format_32bit_index_offset: return 32; + case nir_address_format_vec2_index_32bit_offset: return 32; + case nir_address_format_32bit_offset: return 32; + case nir_address_format_logical: return 32; } unreachable("Invalid address format"); } @@ -4050,12 +4057,13 @@ static inline unsigned nir_address_format_num_components(nir_address_format addr_format) { switch (addr_format) { - case nir_address_format_32bit_global: return 1; - case nir_address_format_64bit_global: return 1; - case nir_address_format_64bit_bounded_global: return 4; - case nir_address_format_32bit_index_offset: return 2; - case nir_address_format_32bit_offset: return 1; - case nir_address_format_logical: return 1; + case nir_address_format_32bit_global: return 1; + case nir_address_format_64bit_global: return 1; + case nir_address_format_64bit_bounded_global: return 4; + case nir_address_format_32bit_index_offset: return 2; + case nir_address_format_vec2_index_32bit_offset: return 3; + case nir_address_format_32bit_offset: return 1; + case nir_address_format_logical: return 1; } unreachable("Invalid address format"); } @@ -4131,6 +4139,7 @@ void nir_lower_io_to_scalar(nir_shader *shader, nir_variable_mode mask); void nir_lower_io_to_scalar_early(nir_shader *shader, nir_variable_mode mask); bool nir_lower_io_to_vector(nir_shader *shader, nir_variable_mode mask); +bool nir_lower_fragcolor(nir_shader *shader); void nir_lower_fragcoord_wtrans(nir_shader *shader); void nir_lower_viewport_transform(nir_shader *shader); bool nir_lower_uniforms_to_ubo(nir_shader *shader, int multiplier); @@ -4144,6 +4153,7 @@ typedef struct nir_lower_subgroups_options { bool lower_subgroup_masks:1; bool lower_shuffle:1; bool lower_shuffle_to_32bit:1; + bool lower_shuffle_to_swizzle_amd:1; bool lower_quad:1; bool lower_quad_broadcast_dynamic:1; bool lower_quad_broadcast_dynamic_to_const:1; @@ -4364,7 +4374,7 @@ void nir_lower_point_size_mov(nir_shader *shader, bool nir_lower_frexp(nir_shader *nir); -void nir_lower_two_sided_color(nir_shader *shader); +void nir_lower_two_sided_color(nir_shader *shader, bool face_sysval); bool nir_lower_clamp_color_outputs(nir_shader *shader); @@ -4455,6 +4465,8 @@ bool nir_lower_interpolation(nir_shader *shader, bool nir_lower_discard_to_demote(nir_shader *shader); +bool nir_lower_memory_model(nir_shader *shader); + bool nir_normalize_cubemap_coords(nir_shader *shader); void nir_live_ssa_defs_impl(nir_function_impl *impl); @@ -4580,21 +4592,6 @@ bool nir_opt_load_store_vectorize(nir_shader *shader, nir_variable_mode modes, nir_should_vectorize_mem_func callback, nir_variable_mode robust_modes); -typedef struct nir_schedule_options { - /* On some hardware with some stages the inputs and outputs to the shader - * share the same memory. In that case scheduler needs to ensure that all - * output writes are scheduled after all of the input writes to avoid - * overwriting them. This is a bitmask of stages that need that. - */ - unsigned stages_with_shared_io_memory; - /* The approximate amount of register pressure at which point the scheduler - * will try to reduce register usage. - */ - int threshold; -} nir_schedule_options; - -void nir_schedule(nir_shader *shader, const nir_schedule_options *options); - void nir_strip(nir_shader *shader); void nir_sweep(nir_shader *shader); @@ -4626,6 +4623,26 @@ nir_variable_is_in_block(const nir_variable *var) return nir_variable_is_in_ubo(var) || nir_variable_is_in_ssbo(var); } +typedef struct nir_unsigned_upper_bound_config { + unsigned min_subgroup_size; + unsigned max_subgroup_size; + unsigned max_work_group_invocations; + unsigned max_work_group_count[3]; + unsigned max_work_group_size[3]; + + uint32_t vertex_attrib_max[32]; +} nir_unsigned_upper_bound_config; + +uint32_t +nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht, + nir_ssa_scalar scalar, + const nir_unsigned_upper_bound_config *config); + +bool +nir_addition_might_overflow(nir_shader *shader, struct hash_table *range_ht, + nir_ssa_scalar ssa, unsigned const_val, + const nir_unsigned_upper_bound_config *config); + #ifdef __cplusplus } /* extern "C" */ #endif