X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcompiler%2Fnir%2Fnir.h;h=16733fd5e5067a9264f5dcf292fb2f340c5efed1;hb=878a8daca6bfc856308dda7d265964d93feb05ae;hp=ecd806523b3054e156c8ceb0aa886372460f5a9c;hpb=70cbddc4a7967c8889f8b10d8a31d7b8bdbde2fb;p=mesa.git

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index ecd806523b3..16733fd5e50 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -121,7 +121,8 @@ typedef enum {
    nir_var_mem_shared      = (1 << 8),
    nir_var_mem_global      = (1 << 9),
    nir_var_mem_push_const  = (1 << 10), /* not actually used for variables */
-   nir_num_variable_modes  = 11,
+   nir_var_mem_constant    = (1 << 11),
+   nir_num_variable_modes  = 12,
    nir_var_all             = (1 << nir_num_variable_modes) - 1,
 } nir_variable_mode;
 MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(nir_variable_mode)
@@ -330,7 +331,7 @@ typedef struct nir_variable {
        *
        * \sa nir_variable_mode
        */
-      unsigned mode:11;
+      unsigned mode:12;
 
       /**
        * Is the variable read-only?
@@ -1461,6 +1462,8 @@ typedef struct {
 
       struct {
          unsigned ptr_stride;
+         unsigned align_mul;
+         unsigned align_offset;
       } cast;
    };
 
@@ -3081,7 +3084,7 @@ typedef struct nir_shader_compiler_options {
    /* lower {slt,sge,seq,sne} to {flt,fge,feq,fneu} + b2f: */
    bool lower_scmp;
 
-   /* lower fall_equalN/fany_nequalN (ex:fany_nequal4 to sne+fdot4+fsat) */
+   /* lower b/fall_equalN/b/fany_nequalN (ex:fany_nequal4 to sne+fdot4+fsat) */
    bool lower_vector_cmp;
 
    /** enables rules to lower idiv by power-of-two: */
@@ -3854,6 +3857,9 @@ void nir_print_shader_annotated(nir_shader *shader, FILE *fp, struct hash_table
 void nir_print_instr(const nir_instr *instr, FILE *fp);
 void nir_print_deref(const nir_deref_instr *deref, FILE *fp);
 
+/** Shallow clone of a single instruction. */
+nir_instr *nir_instr_clone(nir_shader *s, const nir_instr *orig);
+
 /** Shallow clone of a single ALU instruction. */
 nir_alu_instr *nir_alu_instr_clone(nir_shader *s, const nir_alu_instr *orig);
 
@@ -4072,7 +4078,8 @@ typedef enum {
 bool nir_lower_array_deref_of_vec(nir_shader *shader, nir_variable_mode modes,
                                   nir_lower_array_deref_of_vec_options options);
 
-bool nir_lower_indirect_derefs(nir_shader *shader, nir_variable_mode modes);
+bool nir_lower_indirect_derefs(nir_shader *shader, nir_variable_mode modes,
+                               uint32_t max_lower_array_len);
 
 bool nir_lower_locals_to_regs(nir_shader *shader);
 
@@ -4151,6 +4158,9 @@ nir_lower_vars_to_explicit_types(nir_shader *shader,
                                  nir_variable_mode modes,
                                  glsl_type_size_align_func type_info);
 
+bool nir_lower_mem_constant_vars(nir_shader *shader,
+                                 glsl_type_size_align_func type_info);
+
 typedef enum {
    /**
     * An address format which is a simple 32-bit global GPU address.
@@ -4776,7 +4786,10 @@ bool nir_opt_trivial_continues(nir_shader *shader);
 
 bool nir_opt_undef(nir_shader *shader);
 
-bool nir_opt_vectorize(nir_shader *shader);
+typedef bool (*nir_opt_vectorize_cb)(const nir_instr *a, const nir_instr *b,
+                                     void *data);
+bool nir_opt_vectorize(nir_shader *shader, nir_opt_vectorize_cb filter,
+                       void *data);
 
 bool nir_opt_conditional_discard(nir_shader *shader);