X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcompiler%2Fnir%2Fnir.h;h=9feed169e4727ce9f92021fb4ada67edbdc57247;hb=165b7f3a4487e7ab7738dd9b37f2b3375692f8a2;hp=8cdc4ba5707dfc575b8435aca3b01fbd9e0e9026;hpb=d3ce8a7f6b93e893929b81f4d6605a2a968730a1;p=mesa.git diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 8cdc4ba5707..9feed169e47 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -148,7 +148,7 @@ typedef struct nir_constant { * by the type associated with the \c nir_variable. Constants may be * scalars, vectors, or matrices. */ - nir_const_value values[NIR_MAX_MATRIX_COLUMNS][NIR_MAX_VEC_COMPONENTS]; + nir_const_value values[NIR_MAX_VEC_COMPONENTS]; /* we could get this from the var->type but makes clone *much* easier to * not have to care about the type. @@ -848,9 +848,21 @@ nir_get_nir_type_for_glsl_base_type(enum glsl_base_type base_type) case GLSL_TYPE_DOUBLE: return nir_type_float64; break; - default: - unreachable("unknown type"); + + case GLSL_TYPE_SAMPLER: + case GLSL_TYPE_IMAGE: + case GLSL_TYPE_ATOMIC_UINT: + case GLSL_TYPE_STRUCT: + case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_ARRAY: + case GLSL_TYPE_VOID: + case GLSL_TYPE_SUBROUTINE: + case GLSL_TYPE_FUNCTION: + case GLSL_TYPE_ERROR: + return nir_type_invalid; } + + unreachable("unknown type"); } static inline nir_alu_type @@ -862,8 +874,27 @@ nir_get_nir_type_for_glsl_type(const struct glsl_type *type) nir_op nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd); +static inline nir_op +nir_op_vec(unsigned components) +{ + switch (components) { + case 1: return nir_op_mov; + case 2: return nir_op_vec2; + case 3: return nir_op_vec3; + case 4: return nir_op_vec4; + default: unreachable("bad component count"); + } +} + typedef enum { - NIR_OP_IS_COMMUTATIVE = (1 << 0), + /** + * Operation where the first two sources are commutative. + * + * For 2-source operations, this just mathematical commutativity. Some + * 3-source operations, like ffma, are only commutative in the first two + * sources. + */ + NIR_OP_IS_2SRC_COMMUTATIVE = (1 << 0), NIR_OP_IS_ASSOCIATIVE = (1 << 1), } nir_op_algebraic_property; @@ -1041,20 +1072,7 @@ typedef struct { nir_dest dest; } nir_deref_instr; -NIR_DEFINE_CAST(nir_instr_as_deref, nir_instr, nir_deref_instr, instr, - type, nir_instr_type_deref) - -static inline nir_deref_instr * -nir_src_as_deref(nir_src src) -{ - if (!src.is_ssa) - return NULL; - - if (src.ssa->parent_instr->type != nir_instr_type_deref) - return NULL; - - return nir_instr_as_deref(src.ssa->parent_instr); -} +static inline nir_deref_instr *nir_src_as_deref(nir_src src); static inline nir_deref_instr * nir_deref_instr_parent(const nir_deref_instr *instr) @@ -1079,6 +1097,7 @@ nir_deref_instr_get_variable(const nir_deref_instr *instr) } bool nir_deref_instr_has_indirect(nir_deref_instr *instr); +bool nir_deref_instr_has_complex_use(nir_deref_instr *instr); bool nir_deref_instr_remove_if_unused(nir_deref_instr *instr); @@ -1190,80 +1209,80 @@ typedef enum { /** * For store instructions, a writemask for the store. */ - NIR_INTRINSIC_WRMASK = 2, + NIR_INTRINSIC_WRMASK, /** * The stream-id for GS emit_vertex/end_primitive intrinsics. */ - NIR_INTRINSIC_STREAM_ID = 3, + NIR_INTRINSIC_STREAM_ID, /** * The clip-plane id for load_user_clip_plane intrinsic. */ - NIR_INTRINSIC_UCP_ID = 4, + NIR_INTRINSIC_UCP_ID, /** * The amount of data, starting from BASE, that this instruction may * access. This is used to provide bounds if the offset is not constant. */ - NIR_INTRINSIC_RANGE = 5, + NIR_INTRINSIC_RANGE, /** * The Vulkan descriptor set for vulkan_resource_index intrinsic. */ - NIR_INTRINSIC_DESC_SET = 6, + NIR_INTRINSIC_DESC_SET, /** * The Vulkan descriptor set binding for vulkan_resource_index intrinsic. */ - NIR_INTRINSIC_BINDING = 7, + NIR_INTRINSIC_BINDING, /** * Component offset. */ - NIR_INTRINSIC_COMPONENT = 8, + NIR_INTRINSIC_COMPONENT, /** * Interpolation mode (only meaningful for FS inputs). */ - NIR_INTRINSIC_INTERP_MODE = 9, + NIR_INTRINSIC_INTERP_MODE, /** * A binary nir_op to use when performing a reduction or scan operation */ - NIR_INTRINSIC_REDUCTION_OP = 10, + NIR_INTRINSIC_REDUCTION_OP, /** * Cluster size for reduction operations */ - NIR_INTRINSIC_CLUSTER_SIZE = 11, + NIR_INTRINSIC_CLUSTER_SIZE, /** * Parameter index for a load_param intrinsic */ - NIR_INTRINSIC_PARAM_IDX = 12, + NIR_INTRINSIC_PARAM_IDX, /** * Image dimensionality for image intrinsics * * One of GLSL_SAMPLER_DIM_* */ - NIR_INTRINSIC_IMAGE_DIM = 13, + NIR_INTRINSIC_IMAGE_DIM, /** * Non-zero if we are accessing an array image */ - NIR_INTRINSIC_IMAGE_ARRAY = 14, + NIR_INTRINSIC_IMAGE_ARRAY, /** * Image format for image intrinsics */ - NIR_INTRINSIC_FORMAT = 15, + NIR_INTRINSIC_FORMAT, /** * Access qualifiers for image and memory access intrinsics */ - NIR_INTRINSIC_ACCESS = 16, + NIR_INTRINSIC_ACCESS, /** * Alignment for offsets and addresses @@ -1274,13 +1293,28 @@ typedef enum { * * (X - align_offset) % align_mul == 0 */ - NIR_INTRINSIC_ALIGN_MUL = 17, - NIR_INTRINSIC_ALIGN_OFFSET = 18, + NIR_INTRINSIC_ALIGN_MUL, + NIR_INTRINSIC_ALIGN_OFFSET, /** * The Vulkan descriptor type for a vulkan_resource_[re]index intrinsic. */ - NIR_INTRINSIC_DESC_TYPE = 19, + NIR_INTRINSIC_DESC_TYPE, + + /** + * The nir_alu_type of a uniform/input/output + */ + NIR_INTRINSIC_TYPE, + + /** + * The swizzle mask for the instructions + * SwizzleInvocationsAMD and SwizzleInvocationsMaskedAMD + */ + NIR_INTRINSIC_SWIZZLE_MASK, + + /* Separate source/dest access flags for copies */ + NIR_INTRINSIC_SRC_ACCESS = 21, + NIR_INTRINSIC_DST_ACCESS = 22, NIR_INTRINSIC_NUM_INDEX_FLAGS, @@ -1382,10 +1416,14 @@ INTRINSIC_IDX_ACCESSORS(param_idx, PARAM_IDX, unsigned) INTRINSIC_IDX_ACCESSORS(image_dim, IMAGE_DIM, enum glsl_sampler_dim) INTRINSIC_IDX_ACCESSORS(image_array, IMAGE_ARRAY, bool) INTRINSIC_IDX_ACCESSORS(access, ACCESS, enum gl_access_qualifier) +INTRINSIC_IDX_ACCESSORS(src_access, SRC_ACCESS, enum gl_access_qualifier) +INTRINSIC_IDX_ACCESSORS(dst_access, DST_ACCESS, enum gl_access_qualifier) INTRINSIC_IDX_ACCESSORS(format, FORMAT, unsigned) INTRINSIC_IDX_ACCESSORS(align_mul, ALIGN_MUL, unsigned) INTRINSIC_IDX_ACCESSORS(align_offset, ALIGN_OFFSET, unsigned) INTRINSIC_IDX_ACCESSORS(desc_type, DESC_TYPE, unsigned) +INTRINSIC_IDX_ACCESSORS(type, TYPE, nir_alu_type) +INTRINSIC_IDX_ACCESSORS(swizzle_mask, SWIZZLE_MASK, unsigned) static inline void nir_intrinsic_set_align(nir_intrinsic_instr *intrin, @@ -1417,6 +1455,24 @@ nir_intrinsic_align(const nir_intrinsic_instr *intrin) void nir_rewrite_image_intrinsic(nir_intrinsic_instr *instr, nir_ssa_def *handle, bool bindless); +/* Determine if an intrinsic can be arbitrarily reordered and eliminated. */ +static inline bool +nir_intrinsic_can_reorder(nir_intrinsic_instr *instr) +{ + if (instr->intrinsic == nir_intrinsic_load_deref || + instr->intrinsic == nir_intrinsic_load_ssbo || + instr->intrinsic == nir_intrinsic_bindless_image_load || + instr->intrinsic == nir_intrinsic_image_deref_load || + instr->intrinsic == nir_intrinsic_image_load) { + return nir_intrinsic_access(instr) & ACCESS_CAN_REORDER; + } else { + const nir_intrinsic_info *info = + &nir_intrinsic_infos[instr->intrinsic]; + return (info->flags & NIR_INTRINSIC_CAN_ELIMINATE) && + (info->flags & NIR_INTRINSIC_CAN_REORDER); + } +} + /** * \group texture information * @@ -1457,7 +1513,8 @@ typedef enum { nir_texop_txl, /**< Texture look-up with explicit LOD */ nir_texop_txd, /**< Texture look-up with partial derivatives */ nir_texop_txf, /**< Texel fetch with explicit LOD */ - nir_texop_txf_ms, /**< Multisample texture fetch */ + nir_texop_txf_ms, /**< Multisample texture fetch */ + nir_texop_txf_ms_fb, /**< Multisample texture fetch from framebuffer */ nir_texop_txf_ms_mcs, /**< Multisample compression value fetch */ nir_texop_txs, /**< Texture size */ nir_texop_lod, /**< Texture lod query */ @@ -1592,6 +1649,7 @@ nir_tex_instr_is_query(const nir_tex_instr *instr) case nir_texop_txd: case nir_texop_txf: case nir_texop_txf_ms: + case nir_texop_txf_ms_fb: case nir_texop_tg4: return false; default: @@ -1631,6 +1689,7 @@ nir_tex_instr_src_type(const nir_tex_instr *instr, unsigned src) switch (instr->op) { case nir_texop_txf: case nir_texop_txf_ms: + case nir_texop_txf_ms_fb: case nir_texop_txf_ms_mcs: case nir_texop_samples_identical: return nir_type_int; @@ -1793,6 +1852,8 @@ typedef struct { NIR_DEFINE_CAST(nir_instr_as_alu, nir_instr, nir_alu_instr, instr, type, nir_instr_type_alu) +NIR_DEFINE_CAST(nir_instr_as_deref, nir_instr, nir_deref_instr, instr, + type, nir_instr_type_deref) NIR_DEFINE_CAST(nir_instr_as_call, nir_instr, nir_call_instr, instr, type, nir_instr_type_call) NIR_DEFINE_CAST(nir_instr_as_jump, nir_instr, nir_jump_instr, instr, @@ -2138,6 +2199,21 @@ nir_loop_last_block(nir_loop *loop) return nir_cf_node_as_block(exec_node_data(nir_cf_node, tail, node)); } +/** + * Return true if this list of cf_nodes contains a single empty block. + */ +static inline bool +nir_cf_list_is_empty_block(struct exec_list *cf_list) +{ + if (exec_list_is_singular(cf_list)) { + struct exec_node *head = exec_list_get_head(cf_list); + nir_block *block = + nir_cf_node_as_block(exec_node_data(nir_cf_node, head, node)); + return exec_list_is_empty(&block->instr_list); + } + return false; +} + typedef struct { uint8_t num_components; uint8_t bit_size; @@ -2203,23 +2279,19 @@ typedef struct nir_shader_compiler_options { bool lower_fpow; bool lower_fsat; bool lower_fsqrt; - bool lower_fmod16; - bool lower_fmod32; - bool lower_fmod64; + bool lower_fmod; /** Lowers ibitfield_extract/ubitfield_extract to ibfe/ubfe. */ bool lower_bitfield_extract; - /** Lowers ibitfield_extract/ubitfield_extract to bfm, compares, shifts. */ + /** Lowers ibitfield_extract/ubitfield_extract to compares, shifts. */ bool lower_bitfield_extract_to_shifts; /** Lowers bitfield_insert to bfi/bfm */ bool lower_bitfield_insert; - /** Lowers bitfield_insert to bfm, compares, and shifts. */ + /** Lowers bitfield_insert to compares, and shifts. */ bool lower_bitfield_insert_to_shifts; /** Lowers bitfield_reverse to shifts. */ bool lower_bitfield_reverse; /** Lowers bit_count to shifts. */ bool lower_bit_count; - /** Lowers bfm to shifts and subtracts. */ - bool lower_bfm; /** Lowers ifind_msb to compare and ufind_msb */ bool lower_ifind_msb; /** Lowers find_lsb to ufind_msb and logic ops */ @@ -2239,9 +2311,15 @@ typedef struct nir_shader_compiler_options { /** enables rules to lower idiv by power-of-two: */ bool lower_idiv; + /** enable rules to avoid bit shifts */ + bool lower_bitshift; + /** enables rules to lower isign to imin+imax */ bool lower_isign; + /** enables rules to lower fsign to fsub and flt */ + bool lower_fsign; + /* Does the native fdot instruction replicate its result for four * components? If so, then opt_algebraic_late will turn all fdotN * instructions into fdot_replicatedN instructions. @@ -2278,12 +2356,6 @@ typedef struct nir_shader_compiler_options { bool lower_all_io_to_temps; bool lower_all_io_to_elements; - /** - * Does the driver support real 32-bit integers? (Otherwise, integers - * are simulated by floats.) - */ - bool native_integers; - /* Indicates that the driver only has zero-based vertex id */ bool vertex_id_zero_based; @@ -2326,6 +2398,12 @@ typedef struct nir_shader_compiler_options { bool lower_hadd; bool lower_add_sat; + /** + * Should IO be re-vectorized? Some scalar ISAs still operate on vec4's + * for IO purposes and would prefer loads/stores be vectorized. + */ + bool vectorize_io; + /** * Should nir_lower_io() create load_interpolated_input intrinsics? * @@ -2748,27 +2826,18 @@ bool nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state); nir_const_value *nir_src_as_const_value(nir_src src); -static inline struct nir_instr * -nir_src_instr(const struct nir_src *src) -{ - return src->is_ssa ? src->ssa->parent_instr : NULL; -} - #define NIR_SRC_AS_(name, c_type, type_enum, cast_macro) \ static inline c_type * \ -nir_src_as_ ## name (struct nir_src *src) \ -{ \ - return src->is_ssa && src->ssa->parent_instr->type == type_enum \ - ? cast_macro(src->ssa->parent_instr) : NULL; \ -} \ -static inline const c_type * \ -nir_src_as_ ## name ## _const(const struct nir_src *src) \ +nir_src_as_ ## name (nir_src src) \ { \ - return src->is_ssa && src->ssa->parent_instr->type == type_enum \ - ? cast_macro(src->ssa->parent_instr) : NULL; \ + return src.is_ssa && src.ssa->parent_instr->type == type_enum \ + ? cast_macro(src.ssa->parent_instr) : NULL; \ } NIR_SRC_AS_(alu_instr, nir_alu_instr, nir_instr_type_alu, nir_instr_as_alu) +NIR_SRC_AS_(intrinsic, nir_intrinsic_instr, + nir_instr_type_intrinsic, nir_instr_as_intrinsic) +NIR_SRC_AS_(deref, nir_deref_instr, nir_instr_type_deref, nir_instr_as_deref) bool nir_src_is_dynamically_uniform(nir_src src); bool nir_srcs_equal(nir_src src1, nir_src src2); @@ -2867,13 +2936,18 @@ void nir_print_shader_annotated(nir_shader *shader, FILE *fp, struct hash_table void nir_print_instr(const nir_instr *instr, FILE *fp); void nir_print_deref(const nir_deref_instr *deref, FILE *fp); +/** Shallow clone of a single ALU instruction. */ +nir_alu_instr *nir_alu_instr_clone(nir_shader *s, const nir_alu_instr *orig); + nir_shader *nir_shader_clone(void *mem_ctx, const nir_shader *s); nir_function_impl *nir_function_impl_clone(nir_shader *shader, const nir_function_impl *fi); nir_constant *nir_constant_clone(const nir_constant *c, nir_variable *var); nir_variable *nir_variable_clone(const nir_variable *c, nir_shader *shader); -nir_shader *nir_shader_serialize_deserialize(void *mem_ctx, nir_shader *s); +void nir_shader_replace(nir_shader *dest, nir_shader *src); + +void nir_shader_serialize_deserialize(nir_shader *s); #ifndef NDEBUG void nir_validate_shader(nir_shader *shader, const char *when); @@ -2945,12 +3019,10 @@ static inline bool should_print_nir(void) { return false; } nir_validate_shader(nir, "after " #pass); \ if (should_clone_nir()) { \ nir_shader *clone = nir_shader_clone(ralloc_parent(nir), nir); \ - ralloc_free(nir); \ - nir = clone; \ + nir_shader_replace(nir, clone); \ } \ if (should_serialize_deserialize_nir()) { \ - void *mem_ctx = ralloc_parent(nir); \ - nir = nir_shader_serialize_deserialize(mem_ctx, nir); \ + nir_shader_serialize_deserialize(nir); \ } \ } while (0) @@ -3043,6 +3115,10 @@ bool nir_lower_vars_to_scratch(nir_shader *shader, void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint); +void nir_gather_ssa_types(nir_function_impl *impl, + BITSET_WORD *float_types, + BITSET_WORD *int_types); + void nir_assign_var_locations(struct exec_list *var_list, unsigned *size, int (*type_size)(const struct glsl_type *, bool)); @@ -3094,7 +3170,76 @@ typedef enum { * component is a buffer index and the second is an offset. */ nir_address_format_32bit_index_offset, + + /** + * An address format which is a simple 32-bit offset. + */ + nir_address_format_32bit_offset, + + /** + * An address format representing a purely logical addressing model. In + * this model, all deref chains must be complete from the dereference + * operation to the variable. Cast derefs are not allowed. These + * addresses will be 32-bit scalars but the format is immaterial because + * you can always chase the chain. + */ + nir_address_format_logical, } nir_address_format; + +static inline unsigned +nir_address_format_bit_size(nir_address_format addr_format) +{ + switch (addr_format) { + case nir_address_format_32bit_global: return 32; + case nir_address_format_64bit_global: return 64; + case nir_address_format_64bit_bounded_global: return 32; + case nir_address_format_32bit_index_offset: return 32; + case nir_address_format_32bit_offset: return 32; + case nir_address_format_logical: return 32; + } + unreachable("Invalid address format"); +} + +static inline unsigned +nir_address_format_num_components(nir_address_format addr_format) +{ + switch (addr_format) { + case nir_address_format_32bit_global: return 1; + case nir_address_format_64bit_global: return 1; + case nir_address_format_64bit_bounded_global: return 4; + case nir_address_format_32bit_index_offset: return 2; + case nir_address_format_32bit_offset: return 1; + case nir_address_format_logical: return 1; + } + unreachable("Invalid address format"); +} + +static inline const struct glsl_type * +nir_address_format_to_glsl_type(nir_address_format addr_format) +{ + unsigned bit_size = nir_address_format_bit_size(addr_format); + assert(bit_size == 32 || bit_size == 64); + return glsl_vector_type(bit_size == 32 ? GLSL_TYPE_UINT : GLSL_TYPE_UINT64, + nir_address_format_num_components(addr_format)); +} + +const nir_const_value *nir_address_format_null_value(nir_address_format addr_format); + +nir_ssa_def *nir_build_addr_ieq(struct nir_builder *b, nir_ssa_def *addr0, nir_ssa_def *addr1, + nir_address_format addr_format); + +nir_ssa_def *nir_build_addr_isub(struct nir_builder *b, nir_ssa_def *addr0, nir_ssa_def *addr1, + nir_address_format addr_format); + +nir_ssa_def * nir_explicit_io_address_from_deref(struct nir_builder *b, + nir_deref_instr *deref, + nir_ssa_def *base_addr, + nir_address_format addr_format); +void nir_lower_explicit_io_instr(struct nir_builder *b, + nir_intrinsic_instr *io_instr, + nir_ssa_def *addr, + nir_address_format addr_format); + bool nir_lower_explicit_io(nir_shader *shader, nir_variable_mode modes, nir_address_format); @@ -3120,9 +3265,14 @@ bool nir_lower_vec_to_movs(nir_shader *shader); void nir_lower_alpha_test(nir_shader *shader, enum compare_func func, bool alpha_to_one); bool nir_lower_alu(nir_shader *shader); -bool nir_lower_alu_to_scalar(nir_shader *shader); + +bool nir_lower_flrp(nir_shader *shader, unsigned lowering_mask, + bool always_precise, bool have_ffma); + +bool nir_lower_alu_to_scalar(nir_shader *shader, BITSET_WORD *lower_set); bool nir_lower_bool_to_float(nir_shader *shader); bool nir_lower_bool_to_int32(nir_shader *shader); +bool nir_lower_int_to_float(nir_shader *shader); bool nir_lower_load_const_to_scalar(nir_shader *shader); bool nir_lower_read_invocation_to_scalar(nir_shader *shader); bool nir_lower_phis_to_scalar(nir_shader *shader); @@ -3133,6 +3283,7 @@ void nir_lower_io_to_scalar(nir_shader *shader, nir_variable_mode mask); void nir_lower_io_to_scalar_early(nir_shader *shader, nir_variable_mode mask); bool nir_lower_io_to_vector(nir_shader *shader, nir_variable_mode mask); +void nir_lower_fragcoord_wtrans(nir_shader *shader); void nir_lower_viewport_transform(nir_shader *shader); bool nir_lower_uniforms_to_ubo(nir_shader *shader, int multiplier); @@ -3238,6 +3389,12 @@ typedef struct nir_lower_tex_options { */ unsigned lower_srgb; + /** + * If true, lower nir_texop_tex on shaders that doesn't support implicit + * LODs to nir_texop_txl. + */ + bool lower_tex_without_implicit_lod; + /** * If true, lower nir_texop_txd on cube maps with nir_texop_txl. */ @@ -3279,12 +3436,24 @@ typedef struct nir_lower_tex_options { */ bool lower_txd_offset_clamp; + /** + * If true, lower nir_texop_txd with min_lod to a nir_texop_txl if the + * sampler is bindless. + */ + bool lower_txd_clamp_bindless_sampler; + /** * If true, lower nir_texop_txd with min_lod to a nir_texop_txl if the * sampler index is not statically determinable to be less than 16. */ bool lower_txd_clamp_if_sampler_index_not_lt_16; + /** + * If true, lower nir_texop_txs with a non-0-lod into nir_texop_txs with + * 0-lod followed by a nir_ishr. + */ + bool lower_txs_lod; + /** * If true, apply a .bagr swizzle on tg4 results to handle Broadcom's * mixed-up tg4 locations. @@ -3340,6 +3509,8 @@ bool nir_lower_wpos_ytransform(nir_shader *shader, const nir_lower_wpos_ytransform_options *options); bool nir_lower_wpos_center(nir_shader *shader, const bool for_sample_shading); +bool nir_lower_fb_read(nir_shader *shader); + typedef struct nir_lower_drawpixels_options { gl_state_index16 texcoord_state_tokens[STATE_LENGTH]; gl_state_index16 scale_state_tokens[STATE_LENGTH]; @@ -3459,6 +3630,8 @@ bool nir_opt_move_load_ubo(nir_shader *shader); bool nir_opt_peephole_select(nir_shader *shader, unsigned limit, bool indirect_load_ok, bool expensive_alu_ok); +bool nir_opt_rematerialize_compares(nir_shader *shader); + bool nir_opt_remove_phis(nir_shader *shader); bool nir_opt_shrink_load(nir_shader *shader); @@ -3467,6 +3640,8 @@ bool nir_opt_trivial_continues(nir_shader *shader); bool nir_opt_undef(nir_shader *shader); +bool nir_opt_vectorize(nir_shader *shader); + bool nir_opt_conditional_discard(nir_shader *shader); void nir_strip(nir_shader *shader); @@ -3480,6 +3655,8 @@ uint64_t nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot); nir_intrinsic_op nir_intrinsic_from_system_value(gl_system_value val); gl_system_value nir_system_value_from_intrinsic(nir_intrinsic_op intrin); +bool nir_lower_sincos(nir_shader *shader); + #ifdef __cplusplus } /* extern "C" */ #endif