X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2FBaseCPU.py;h=4661375ba4486bbcba38c60c9cfe22b71e035ac0;hb=d85cd08113e61817fdf1df978f2713ba8b094996;hp=3aa9b87bb5f8ab6516be3230eca172afbe9c930c;hpb=e0de2c34433be76eac7798e58e1ae02f5bffb732;p=gem5.git

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 3aa9b87bb..4661375ba 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips':
     if build_env['FULL_SYSTEM']:
         from MipsInterrupts import MipsInterrupts
 elif build_env['TARGET_ISA'] == 'arm':
-    from ArmTLB import ArmDTB
+    from ArmTLB import ArmTLB
     if build_env['FULL_SYSTEM']:
         from ArmInterrupts import ArmInterrupts
 
@@ -109,8 +109,8 @@ class BaseCPU(MemObject):
                     MipsInterrupts(), "Interrupt Controller")
     elif build_env['TARGET_ISA'] == 'arm':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
-        dtb = Param.ArmTLB(ArmDTB(), "Data TLB")
-        itb = Param.ArmTLB(ArmITB(), "Instruction TLB")
+        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
+        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
         if build_env['FULL_SYSTEM']:
             interrupts = Param.ArmInterrupts(
                     ArmInterrupts(), "Interrupt Controller")