X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2FBaseCPU.py;h=ac734e5ac409c0282d5386c6ef8546884f210125;hb=eac5eac67ae8076e934d78063a24eeef08f25413;hp=c2a86511341d29d37a0f39f300be0e737fc8242b;hpb=0ccf9a2c3751f160d7d51153ef468a60b4daf8d0;p=gem5.git diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c2a865113..ac734e5ac 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -26,66 +26,110 @@ # # Authors: Nathan Binkert -from m5.SimObject import SimObject +import sys + +from m5.defines import buildEnv from m5.params import * from m5.proxy import * -from m5 import build_env + from Bus import Bus from InstTracer import InstTracer from ExeTracer import ExeTracer -import sys +from MemObject import MemObject default_tracer = ExeTracer() -if build_env['TARGET_ISA'] == 'alpha': +if buildEnv['TARGET_ISA'] == 'alpha': from AlphaTLB import AlphaDTB, AlphaITB -elif build_env['TARGET_ISA'] == 'sparc': - from SparcTLB import SparcDTB, SparcITB -elif build_env['TARGET_ISA'] == 'x86': - from X86TLB import X86DTB, X86ITB -elif build_env['TARGET_ISA'] == 'mips': - from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB -elif build_env['TARGET_ISA'] == 'arm': - from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB - -class BaseCPU(SimObject): + if buildEnv['FULL_SYSTEM']: + from AlphaInterrupts import AlphaInterrupts +elif buildEnv['TARGET_ISA'] == 'sparc': + from SparcTLB import SparcTLB + if buildEnv['FULL_SYSTEM']: + from SparcInterrupts import SparcInterrupts +elif buildEnv['TARGET_ISA'] == 'x86': + from X86TLB import X86TLB + if buildEnv['FULL_SYSTEM']: + from X86LocalApic import X86LocalApic +elif buildEnv['TARGET_ISA'] == 'mips': + from MipsTLB import MipsTLB + if buildEnv['FULL_SYSTEM']: + from MipsInterrupts import MipsInterrupts +elif buildEnv['TARGET_ISA'] == 'arm': + from ArmTLB import ArmTLB + if buildEnv['FULL_SYSTEM']: + from ArmInterrupts import ArmInterrupts +elif buildEnv['TARGET_ISA'] == 'power': + from PowerTLB import PowerTLB + if buildEnv['FULL_SYSTEM']: + from PowerInterrupts import PowerInterrupts + +class BaseCPU(MemObject): type = 'BaseCPU' abstract = True system = Param.System(Parent.any, "system object") - cpu_id = Param.Int("CPU identifier") + cpu_id = Param.Int(-1, "CPU identifier") + numThreads = Param.Unsigned(1, "number of HW thread contexts") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + + checker = Param.BaseCPU(NULL, "checker CPU") + + do_checkpoint_insts = Param.Bool(True, + "enable checkpoint pseudo instructions") + do_statistics_insts = Param.Bool(True, + "enable statistics pseudo instructions") - if build_env['FULL_SYSTEM']: + if buildEnv['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") - do_checkpoint_insts = Param.Bool(True, - "enable checkpoint pseudo instructions") - do_statistics_insts = Param.Bool(True, - "enable statistics pseudo instructions") else: workload = VectorParam.Process("processes to run") - if build_env['TARGET_ISA'] == 'sparc': - dtb = Param.SparcDTB(SparcDTB(), "Data TLB") - itb = Param.SparcITB(SparcITB(), "Instruction TLB") - elif build_env['TARGET_ISA'] == 'alpha': - dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") - itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") - elif build_env['TARGET_ISA'] == 'x86': - dtb = Param.X86DTB(X86DTB(), "Data TLB") - itb = Param.X86ITB(X86ITB(), "Instruction TLB") - elif build_env['TARGET_ISA'] == 'mips': + if buildEnv['TARGET_ISA'] == 'sparc': + dtb = Param.SparcTLB(SparcTLB(), "Data TLB") + itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + interrupts = Param.SparcInterrupts( + SparcInterrupts(), "Interrupt Controller") + elif buildEnv['TARGET_ISA'] == 'alpha': + dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") + itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + interrupts = Param.AlphaInterrupts( + AlphaInterrupts(), "Interrupt Controller") + elif buildEnv['TARGET_ISA'] == 'x86': + dtb = Param.X86TLB(X86TLB(), "Data TLB") + itb = Param.X86TLB(X86TLB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + _localApic = X86LocalApic(pio_addr=0x2000000000000000) + interrupts = \ + Param.X86LocalApic(_localApic, "Interrupt Controller") + elif buildEnv['TARGET_ISA'] == 'mips': + dtb = Param.MipsTLB(MipsTLB(), "Data TLB") + itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + interrupts = Param.MipsInterrupts( + MipsInterrupts(), "Interrupt Controller") + elif buildEnv['TARGET_ISA'] == 'arm': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") - dtb = Param.MipsDTB(MipsDTB(), "Data TLB") - itb = Param.MipsITB(MipsITB(), "Instruction TLB") - tlb = Param.MipsUTB(MipsUTB(), "Unified TLB") - elif build_env['TARGET_ISA'] == 'arm': + dtb = Param.ArmTLB(ArmTLB(), "Data TLB") + itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + interrupts = Param.ArmInterrupts( + ArmInterrupts(), "Interrupt Controller") + elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") - dtb = Param.ArmDTB(ArmDTB(), "Data TLB") - itb = Param.ArmITB(ArmITB(), "Instruction TLB") - tlb = Param.ArmUTB(ArmUTB(), "Unified TLB") + dtb = Param.PowerTLB(PowerTLB(), "Data TLB") + itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + interrupts = Param.PowerInterrupts( + PowerInterrupts(), "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ - build_env['TARGET_ISA'] + buildEnv['TARGET_ISA'] sys.exit(1) max_insts_all_threads = Param.Counter(0, @@ -108,8 +152,11 @@ class BaseCPU(SimObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") _mem_ports = [] - if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - _mem_ports = ["itb.walker.port", "dtb.walker.port"] + if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: + _mem_ports = ["itb.walker.port", + "dtb.walker.port", + "interrupts.pio", + "interrupts.int_port"] def connectMemPorts(self, bus): for p in self._mem_ports: @@ -123,7 +170,7 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] - if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: self._mem_ports += ["itb.walker_port", "dtb.walker_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): @@ -134,7 +181,7 @@ class BaseCPU(SimObject): self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] - if build_env['TARGET_ISA'] == 'mips': + if buildEnv['TARGET_ISA'] == 'mips': CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")