X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2FBaseCPU.py;h=c85e5afda7ed3d806ca1c45abbdea2eca1ba1975;hb=e76bfc87640dd236f1527e3f8f19507f0275dad9;hp=4d114cbdcecb3db1faea955664af82f9bdd20965;hpb=ce2722cdd97a31f85d36f6c32637b230e3c25c73;p=gem5.git

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 4d114cbdc..c85e5afda 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -85,6 +85,11 @@ elif buildEnv['TARGET_ISA'] == 'power':
     from PowerInterrupts import PowerInterrupts
     from PowerISA import PowerISA
     isa_class = PowerISA
+elif buildEnv['TARGET_ISA'] == 'riscv':
+    from RiscvTLB import RiscvTLB
+    from RiscvInterrupts import RiscvInterrupts
+    from RiscvISA import RiscvISA
+    isa_class = RiscvISA
 
 class BaseCPU(MemObject):
     type = 'BaseCPU'
@@ -185,6 +190,12 @@ class BaseCPU(MemObject):
         interrupts = VectorParam.PowerInterrupts(
                 [], "Interrupt Controller")
         isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
+    elif buildEnv['TARGET_ISA'] == 'riscv':
+        dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
+        itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
+        interrupts = VectorParam.RiscvInterrupts(
+                [], "Interrupt Controller")
+        isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             buildEnv['TARGET_ISA']
@@ -242,6 +253,9 @@ class BaseCPU(MemObject):
             self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
         elif buildEnv['TARGET_ISA'] == 'power':
             self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
+        elif buildEnv['TARGET_ISA'] == 'riscv':
+            self.interrupts = \
+                [RiscvInterrupts() for i in xrange(self.numThreads)]
         else:
             print "Don't know what Interrupt Controller to use for ISA %s" % \
                 buildEnv['TARGET_ISA']