X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2FSConscript;h=df29f6c73d0e7adac0feb397f2c6293f70a9650b;hb=a384525355c37f8776e03c78e12279c38c5c3097;hp=ea79b622c7e7f24033b29cf55954047d7344f04f;hpb=225de2eaff57bdf27d367531f25a654e4cd06fe6;p=gem5.git diff --git a/src/cpu/SConscript b/src/cpu/SConscript index ea79b622c..df29f6c73 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -30,152 +30,87 @@ Import('*') -################################################################# -# -# Generate StaticInst execute() method signatures. -# -# There must be one signature for each CPU model compiled in. -# Since the set of compiled-in models is flexible, we generate a -# header containing the appropriate set of signatures on the fly. -# -################################################################# - -# CPU model-specific data is contained in cpu_models.py -# Convert to SCons File node to get path handling -models_db = File('cpu_models.py') -# slurp in contents of file -execfile(models_db.srcnode().abspath) - -# Template for execute() signature. -exec_sig_template = ''' -virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; -virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const -{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; -virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const -{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; -virtual Fault completeAcc(Packet *pkt, %(type)s *xc, - Trace::InstRecord *traceData) const -{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; -''' - -mem_ini_sig_template = ''' -virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const -{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; -virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; -''' - -mem_comp_sig_template = ''' -virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; -''' - -# Generate a temporary CPU list, including the CheckerCPU if -# it's enabled. This isn't used for anything else other than StaticInst -# headers. -temp_cpu_list = env['CPU_MODELS'][:] - -if env['USE_CHECKER']: - temp_cpu_list.append('CheckerCPU') - SimObject('CheckerCPU.py') - -# Generate header. -def gen_cpu_exec_signatures(target, source, env): - f = open(str(target[0]), 'w') - print >> f, ''' -#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ -#define __CPU_STATIC_INST_EXEC_SIGS_HH__ -''' - for cpu in temp_cpu_list: - xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] - print >> f, exec_sig_template % { 'type' : xc_type } - print >> f, ''' -#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ -''' - -# Generate string that gets printed when header is rebuilt -def gen_sigs_string(target, source, env): - return "Generating static_inst_exec_sigs.hh: " \ - + ', '.join(temp_cpu_list) - -# Add command to generate header to environment. -env.Command('static_inst_exec_sigs.hh', models_db, - Action(gen_cpu_exec_signatures, gen_sigs_string, - varlist = temp_cpu_list)) - -env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) -env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) +if env['TARGET_ISA'] == 'null': + SimObject('IntrControl.py') + Source('intr_control_noisa.cc') + Return() -# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True -# and one of these are not being used. -CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] +SimObject('CheckerCPU.py') SimObject('BaseCPU.py') SimObject('FuncUnit.py') SimObject('ExeTracer.py') SimObject('IntelTrace.py') +SimObject('IntrControl.py') SimObject('NativeTrace.py') +SimObject('TimingExpr.py') Source('activity.cc') Source('base.cc') Source('cpuevent.cc') Source('exetrace.cc') +Source('exec_context.cc') Source('func_unit.cc') Source('inteltrace.cc') +Source('intr_control.cc') Source('nativetrace.cc') Source('pc_event.cc') +Source('profile.cc') Source('quiesce_event.cc') +Source('reg_class.cc') Source('static_inst.cc') Source('simple_thread.cc') Source('thread_context.cc') Source('thread_state.cc') - -if env['FULL_SYSTEM']: - SimObject('IntrControl.py') - - Source('intr_control.cc') - Source('profile.cc') - - if env['TARGET_ISA'] == 'sparc': - SimObject('LegionTrace.py') - Source('legiontrace.cc') - -if env['USE_CHECKER']: - Source('checker/cpu.cc') - TraceFlag('Checker') - checker_supports = False - for i in CheckerSupportedCPUList: - if i in env['CPU_MODELS']: - checker_supports = True - if not checker_supports: - print "Checker only supports CPU models", - for i in CheckerSupportedCPUList: - print i, - print ", please set USE_CHECKER=False or use one of those CPU models" - Exit(1) - -TraceFlag('Activity') -TraceFlag('Commit') -TraceFlag('Context') -TraceFlag('Decode') -TraceFlag('DynInst') -TraceFlag('ExecEnable') -TraceFlag('ExecCPSeq') -TraceFlag('ExecEffAddr') -TraceFlag('ExecFetchSeq') -TraceFlag('ExecOpClass') -TraceFlag('ExecRegDelta') -TraceFlag('ExecResult') -TraceFlag('ExecSpeculative') -TraceFlag('ExecSymbol') -TraceFlag('ExecThread') -TraceFlag('ExecTicks') -TraceFlag('ExecMicro') -TraceFlag('ExecMacro') -TraceFlag('Fetch') -TraceFlag('IntrControl') -TraceFlag('PCEvent') -TraceFlag('Quiesce') - +Source('timing_expr.cc') + +if env['TARGET_ISA'] == 'sparc': + SimObject('LegionTrace.py') + Source('legiontrace.cc') + +SimObject('DummyChecker.py') +SimObject('StaticInstFlags.py') +Source('checker/cpu.cc') +Source('dummy_checker.cc') +DebugFlag('Checker') + +DebugFlag('Activity') +DebugFlag('Commit') +DebugFlag('Context') +DebugFlag('Decode') +DebugFlag('DynInst') +DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)') +DebugFlag('ExecCPSeq', 'Format: Instruction sequence number') +DebugFlag('ExecEffAddr', 'Format: Include effective address') +DebugFlag('ExecFaulting', 'Trace faulting instructions') +DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number') +DebugFlag('ExecOpClass', 'Format: Include operand class') +DebugFlag('ExecRegDelta') +DebugFlag('ExecResult', 'Format: Include results from execution') +DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)') +DebugFlag('ExecSymbol', 'Format: Try to include symbol names') +DebugFlag('ExecThread', 'Format: Include thread ID in trace') +DebugFlag('ExecTicks', 'Format: Include tick count') +DebugFlag('ExecMicro', 'Filter: Include microops') +DebugFlag('ExecMacro', 'Filter: Include macroops') +DebugFlag('ExecUser', 'Filter: Trace user mode instructions') +DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') +DebugFlag('ExecAsid', 'Format: Include ASID in trace') +DebugFlag('ExecFlags', 'Format: Include instruction flags in trace') +DebugFlag('Fetch') +DebugFlag('IntrControl') +DebugFlag('O3PipeView') +DebugFlag('PCEvent') +DebugFlag('Quiesce') + +CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', + 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', + 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread', + 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', + 'ExecAsid', 'ExecFlags' ]) CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', - 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ]) + 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting', + 'ExecUser', 'ExecKernel' ]) CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', - 'ExecEffAddr', 'ExecResult', 'ExecMicro' ]) + 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting', + 'ExecUser', 'ExecKernel' ])