X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2FStaticInstFlags.py;h=b70f919b046330c9ce55f26ae0e6b8699b550365;hb=d64465c02482fc2afa4c1467650976856c9a440a;hp=55ef456ce4a218af6303aa34908e5a5297e73589;hpb=166da650a3c864b31193ade893ed99e547c67644;p=gem5.git

diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 55ef456ce..b70f919b0 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -1,3 +1,4 @@
+# Copyright (c) 2020 ARM Limited
 # Copyright (c) 2003-2005 The Regents of The University of Michigan
 # Copyright (c) 2013 Advanced Micro Devices, Inc.
 # All rights reserved.
@@ -24,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
 
 from m5.params import *
 
@@ -64,6 +63,7 @@ class StaticInstFlags(Enum):
         'IsMemRef',         # References memory (load, store, or prefetch)
         'IsLoad',           # Reads from memory (load or prefetch).
         'IsStore',          # Writes to memory.
+        'IsAtomic',         # Does atomic RMW to memory.
         'IsStoreConditional',   # Store conditional instruction.
         'IsIndexed',        # Accesses memory with an indexed address
                             # computation
@@ -78,10 +78,6 @@ class StaticInstFlags(Enum):
         'IsCall',           # Subroutine call.
         'IsReturn',         # Subroutine return.
 
-        'IsCondDelaySlot',  # Conditional Delay-Slot Instruction
-
-        'IsThreadSync',     # Thread synchronization operation.
-
         'IsSerializing',    # Serializes pipeline: won't execute until all
                             # older instructions have committed.
         'IsSerializeBefore',
@@ -89,7 +85,6 @@ class StaticInstFlags(Enum):
         'IsMemBarrier',     # Is a memory barrier
         'IsWriteBarrier',   # Is a write barrier
         'IsReadBarrier',    # Is a read barrier
-        'IsERET',           # <- Causes the IFU to stall (MIPS ISA)
 
         'IsNonSpeculative', # Should not be executed speculatively
         'IsQuiesce',        # Is a quiesce instruction
@@ -110,5 +105,9 @@ class StaticInstFlags(Enum):
         'IsMicroBranch',    # This microop branches within the microcode for
                             # a macroop
         'IsDspOp',
-        'IsSquashAfter'     # Squash all uncommitted state after executed
+        'IsSquashAfter',     # Squash all uncommitted state after executed
+        # hardware transactional memory
+        'IsHtmStart',       # Starts a HTM transaction
+        'IsHtmStop',        # Stops (commits) a HTM transaction
+        'IsHtmCancel'       # Explicitely aborts a HTM transaction
         ]