X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fbase.hh;h=83d73ede04cbd77d029fef92fbe87fcfc3a89bba;hb=909380f3ee576f915f52c6245c59d41050a46f49;hp=9257778ef7f30030bc44750c511daadba13ed9c5;hpb=b5e68fb54677f601bb00c23af52db8fd6571301f;p=gem5.git diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 9257778ef..83d73ede0 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -34,22 +34,30 @@ #include +#include "arch/isa_traits.hh" +#include "arch/microcode_rom.hh" #include "base/statistics.hh" #include "config/full_system.hh" #include "sim/eventq.hh" +#include "sim/insttracer.hh" #include "mem/mem_object.hh" -#include "arch/isa_traits.hh" #if FULL_SYSTEM #include "arch/interrupts.hh" #endif +class BaseCPUParams; class BranchPred; class CheckerCPU; class ThreadContext; class System; class Port; +namespace TheISA +{ + class Predecoder; +} + class CPUProgressEvent : public Event { protected: @@ -58,11 +66,11 @@ class CPUProgressEvent : public Event BaseCPU *cpu; public: - CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); + CPUProgressEvent(BaseCPU *_cpu, Tick ival); void process(); - virtual const char *description(); + virtual const char *description() const; }; class BaseCPU : public MemObject @@ -70,12 +78,25 @@ class BaseCPU : public MemObject protected: // CPU's clock period in terms of the number of ticks of curTime. Tick clock; + // @todo remove me after debugging with legion done + Tick instCnt; + // every cpu has an id, put it in the base cpu + // Set at initialization, only time a cpuId might change is during a + // takeover (which should be done from within the BaseCPU anyway, + // therefore no setCpuId() method is provided + int _cpuId; public: + /** Reads this CPU's ID. */ + int cpuId() { return _cpuId; } + // Tick currentTick; inline Tick frequency() const { return Clock::Frequency / clock; } - inline Tick cycles(int numCycles) const { return clock * numCycles; } + inline Tick ticks(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } + inline Tick tickToCycles(Tick val) const { return val / clock; } + // @todo remove me after debugging with legion done + Tick instCount() { return instCnt; } /** The next cycle the CPU should be scheduled, given a cache * access or quiesce event returning on this cycle. This function @@ -91,29 +112,37 @@ class BaseCPU : public MemObject */ Tick nextCycle(Tick begin_tick); + TheISA::MicrocodeRom microcodeRom; + #if FULL_SYSTEM protected: -// uint64_t interrupts[TheISA::NumInterruptLevels]; -// uint64_t intstatus; - TheISA::Interrupts interrupts; + TheISA::Interrupts *interrupts; public: - virtual void post_interrupt(int int_num, int index); - virtual void clear_interrupt(int int_num, int index); - virtual void clear_interrupts(); - bool checkInterrupts; + TheISA::Interrupts * + getInterruptController() + { + return interrupts; + } + + virtual void postInterrupt(int int_num, int index); + virtual void clearInterrupt(int int_num, int index); + virtual void clearInterrupts(); - bool check_interrupts(ThreadContext * tc) const - { return interrupts.check_interrupts(tc); } + bool + checkInterrupts(ThreadContext *tc) const + { + return interrupts->checkInterrupts(tc); + } class ProfileEvent : public Event { private: BaseCPU *cpu; - int interval; + Tick interval; public: - ProfileEvent(BaseCPU *cpu, int interval); + ProfileEvent(BaseCPU *cpu, Tick interval); void process(); }; ProfileEvent *profileEvent; @@ -121,9 +150,15 @@ class BaseCPU : public MemObject protected: std::vector threadContexts; + std::vector predecoders; + + Trace::InstTracer * tracer; public: + /// Provide access to the tracer pointer + Trace::InstTracer * getTracer() { return tracer; } + /// Notify the CPU that the indicated context is now active. The /// delay parameter indicates the number of ticks to wait before /// executing (typically 0 or 1). @@ -138,32 +173,16 @@ class BaseCPU : public MemObject /// Notify the CPU that the indicated context is now halted. virtual void haltContext(int thread_num) {} - public: - struct Params - { - std::string name; - int numberOfThreads; - bool deferRegistration; - Counter max_insts_any_thread; - Counter max_insts_all_threads; - Counter max_loads_any_thread; - Counter max_loads_all_threads; - Tick clock; - bool functionTrace; - Tick functionTraceStart; - System *system; - int cpu_id; -#if FULL_SYSTEM - Tick profile; -#endif - Tick progress_interval; - BaseCPU *checker; + /// Given a Thread Context pointer return the thread num + int findContext(ThreadContext *tc); - Params(); - }; - - const Params *params; + /// Given a thread num get tho thread context for it + ThreadContext *getContext(int tn) { return threadContexts[tn]; } + public: + typedef BaseCPUParams Params; + const Params *params() const + { return reinterpret_cast(_params); } BaseCPU(Params *params); virtual ~BaseCPU(); @@ -181,7 +200,7 @@ class BaseCPU : public MemObject /// Take over execution from the given CPU. Used for warm-up and /// sampling. - virtual void takeOverFrom(BaseCPU *); + virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); /** * Number of threads we're actually simulating (<= SMT_MAX_THREADS). @@ -189,6 +208,8 @@ class BaseCPU : public MemObject */ int number_of_threads; + TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core + /** * Vector of per-thread instruction-based event queues. Used for * scheduling events based on number of instructions committed by @@ -205,6 +226,8 @@ class BaseCPU : public MemObject System *system; + Tick phase; + #if FULL_SYSTEM /** * Serialize this object to the given output stream.