X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fbase.hh;h=cc3f861cca93583fd66f19d7f82597204bff1b52;hb=f34a8f0d6163fe82849d494bf78c0f5ec175861c;hp=93e5476ef6667293cf658d292aa6ea27a6c2f2f2;hpb=8aaa39e93dfe000ad423b585e78a4c2ee7418363;p=gem5.git diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 93e5476ef..cc3f861cc 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -48,27 +48,25 @@ #include +// Before we do anything else, check if this build is the NULL ISA, +// and if so stop here +#include "config/the_isa.hh" +#if THE_ISA == NULL_ISA +#include "arch/null/cpu_dummy.hh" +#else #include "arch/interrupts.hh" #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" -#include "config/the_isa.hh" #include "mem/mem_object.hh" #include "sim/eventq.hh" #include "sim/full_system.hh" #include "sim/insttracer.hh" +#include "sim/system.hh" -class BaseCPUParams; -class BranchPred; +struct BaseCPUParams; class CheckerCPU; class ThreadContext; -class System; -class Port; - -namespace TheISA -{ - class Predecoder; -} class CPUProgressEvent : public Event { @@ -94,8 +92,7 @@ class CPUProgressEvent : public Event class BaseCPU : public MemObject { protected: - // CPU's clock period in terms of the number of ticks of curTime. - Tick clock; + // @todo remove me after debugging with legion done Tick instCnt; // every cpu has an id, put it in the base cpu @@ -104,81 +101,91 @@ class BaseCPU : public MemObject // therefore no setCpuId() method is provided int _cpuId; + /** Each cpu will have a socket ID that corresponds to its physical location + * in the system. This is usually used to bucket cpu cores under single DVFS + * domain. This information may also be required by the OS to identify the + * cpu core grouping (as in the case of ARM via MPIDR register) + */ + const uint32_t _socketId; + /** instruction side request id that must be placed in all requests */ MasterID _instMasterId; /** data side request id that must be placed in all requests */ MasterID _dataMasterId; - /** - * Define a base class for the CPU ports (instruction and data) - * that is refined in the subclasses. This class handles the - * common cases, i.e. the functional accesses and the status - * changes and address range queries. The default behaviour for - * both atomic and timing access is to panic and the corresponding - * subclasses have to override these methods. + /** An intrenal representation of a task identifier within gem5. This is + * used so the CPU can add which taskId (which is an internal representation + * of the OS process ID) to each request so components in the memory system + * can track which process IDs are ultimately interacting with them */ - class CpuPort : public Port - { - public: - - /** - * Create a CPU port with a name and a structural owner. - * - * @param _name port name including the owner - * @param _name structural owner of this port - */ - CpuPort(const std::string& _name, MemObject* _owner) : - Port(_name, _owner) - { } + uint32_t _taskId; - protected: + /** The current OS process ID that is executing on this processor. This is + * used to generate a taskId */ + uint32_t _pid; - virtual bool recvTiming(PacketPtr pkt); + /** Is the CPU switched out or active? */ + bool _switchedOut; - virtual Tick recvAtomic(PacketPtr pkt); + /** Cache the cache line size that we get from the system */ + const unsigned int _cacheLineSize; - virtual void recvRetry(); - - void recvFunctional(PacketPtr pkt); + public: - void recvRangeChange(); + /** + * Purely virtual method that returns a reference to the data + * port. All subclasses must implement this method. + * + * @return a reference to the data port + */ + virtual MasterPort &getDataPort() = 0; - }; + /** + * Purely virtual method that returns a reference to the instruction + * port. All subclasses must implement this method. + * + * @return a reference to the instruction port + */ + virtual MasterPort &getInstPort() = 0; - public: /** Reads this CPU's ID. */ - int cpuId() { return _cpuId; } + int cpuId() const { return _cpuId; } + + /** Reads this CPU's Socket ID. */ + uint32_t socketId() const { return _socketId; } /** Reads this CPU's unique data requestor ID */ MasterID dataMasterId() { return _dataMasterId; } /** Reads this CPU's unique instruction requestor ID */ MasterID instMasterId() { return _instMasterId; } -// Tick currentTick; - inline Tick frequency() const { return SimClock::Frequency / clock; } - inline Tick ticks(int numCycles) const { return clock * numCycles; } - inline Tick curCycle() const { return curTick() / clock; } - inline Tick tickToCycles(Tick val) const { return val / clock; } + /** + * Get a master port on this CPU. All CPUs have a data and + * instruction port, and this method uses getDataPort and + * getInstPort of the subclasses to resolve the two ports. + * + * @param if_name the port name + * @param idx ignored index + * + * @return a reference to the port with the given name + */ + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); + + /** Get cpu task id */ + uint32_t taskId() const { return _taskId; } + /** Set cpu task id */ + void taskId(uint32_t id) { _taskId = id; } + + uint32_t getPid() const { return _pid; } + void setPid(uint32_t pid) { _pid = pid; } + inline void workItemBegin() { numWorkItemsStarted++; } inline void workItemEnd() { numWorkItemsCompleted++; } // @todo remove me after debugging with legion done Tick instCount() { return instCnt; } - /** The next cycle the CPU should be scheduled, given a cache - * access or quiesce event returning on this cycle. This function - * may return curTick() if the CPU should run on the current cycle. - */ - Tick nextCycle(); - - /** The next cycle the CPU should be scheduled, given a cache - * access or quiesce event returning on the given Tick. This - * function may return curTick() if the CPU should run on the - * current cycle. - * @param begin_tick The tick that the event is completing on. - */ - Tick nextCycle(Tick begin_tick); - TheISA::MicrocodeRom microcodeRom; protected: @@ -233,7 +240,6 @@ class BaseCPU : public MemObject protected: std::vector threadContexts; - std::vector predecoders; Trace::InstTracer * tracer; @@ -248,7 +254,7 @@ class BaseCPU : public MemObject /// Notify the CPU that the indicated context is now active. The /// delay parameter indicates the number of ticks to wait before /// executing (typically 0 or 1). - virtual void activateContext(ThreadID thread_num, int delay) {} + virtual void activateContext(ThreadID thread_num, Cycles delay) {} /// Notify the CPU that the indicated context is now suspended. virtual void suspendContext(ThreadID thread_num) {} @@ -263,13 +269,16 @@ class BaseCPU : public MemObject int findContext(ThreadContext *tc); /// Given a thread num get tho thread context for it - ThreadContext *getContext(int tn) { return threadContexts[tn]; } + virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } + + /// Get the number of thread contexts available + unsigned numContexts() { return threadContexts.size(); } public: typedef BaseCPUParams Params; const Params *params() const { return reinterpret_cast(_params); } - BaseCPU(Params *params); + BaseCPU(Params *params, bool is_checker = false); virtual ~BaseCPU(); virtual void init(); @@ -280,13 +289,56 @@ class BaseCPU : public MemObject void registerThreadContexts(); - /// Prepare for another CPU to take over execution. When it is - /// is ready (drained pipe) it signals the sampler. + /** + * Prepare for another CPU to take over execution. + * + * When this method exits, all internal state should have been + * flushed. After the method returns, the simulator calls + * takeOverFrom() on the new CPU with this CPU as its parameter. + */ virtual void switchOut(); - /// Take over execution from the given CPU. Used for warm-up and - /// sampling. - virtual void takeOverFrom(BaseCPU *); + /** + * Load the state of a CPU from the previous CPU object, invoked + * on all new CPUs that are about to be switched in. + * + * A CPU model implementing this method is expected to initialize + * its state from the old CPU and connect its memory (unless they + * are already connected) to the memories connected to the old + * CPU. + * + * @param cpu CPU to initialize read state from. + */ + virtual void takeOverFrom(BaseCPU *cpu); + + /** + * Flush all TLBs in the CPU. + * + * This method is mainly used to flush stale translations when + * switching CPUs. It is also exported to the Python world to + * allow it to request a TLB flush after draining the CPU to make + * it easier to compare traces when debugging + * handover/checkpointing. + */ + void flushTLBs(); + + /** + * Determine if the CPU is switched out. + * + * @return True if the CPU is switched out, false otherwise. + */ + bool switchedOut() const { return _switchedOut; } + + /** + * Verify that the system is in a memory mode supported by the + * CPU. + * + * Implementations are expected to query the system for the + * current memory mode and ensure that it is what the CPU model + * expects. If the check fails, the implementation should + * terminate the simulation using fatal(). + */ + virtual void verifyMemoryMode() const { }; /** * Number of threads we're actually simulating (<= SMT_MAX_THREADS). @@ -310,28 +362,87 @@ class BaseCPU : public MemObject System *system; - Tick phase; + /** + * Get the cache line size of the system. + */ + inline unsigned int cacheLineSize() const { return _cacheLineSize; } /** * Serialize this object to the given output stream. + * + * @note CPU models should normally overload the serializeThread() + * method instead of the serialize() method as this provides a + * uniform data format for all CPU models and promotes better code + * reuse. + * * @param os The stream to serialize to. */ virtual void serialize(std::ostream &os); /** * Reconstruct the state of this object from a checkpoint. + * + * @note CPU models should normally overload the + * unserializeThread() method instead of the unserialize() method + * as this provides a uniform data format for all CPU models and + * promotes better code reuse. + * @param cp The checkpoint use. - * @param section The section name of this object + * @param section The section name of this object. */ virtual void unserialize(Checkpoint *cp, const std::string §ion); /** - * Return pointer to CPU's branch predictor (NULL if none). - * @return Branch predictor pointer. + * Serialize a single thread. + * + * @param os The stream to serialize to. + * @param tid ID of the current thread. + */ + virtual void serializeThread(std::ostream &os, ThreadID tid) {}; + + /** + * Unserialize one thread. + * + * @param cp The checkpoint use. + * @param section The section name of this thread. + * @param tid ID of the current thread. + */ + virtual void unserializeThread(Checkpoint *cp, const std::string §ion, + ThreadID tid) {}; + + virtual Counter totalInsts() const = 0; + + virtual Counter totalOps() const = 0; + + /** + * Schedule an event that exits the simulation loops after a + * predefined number of instructions. + * + * This method is usually called from the configuration script to + * get an exit event some time in the future. It is typically used + * when the script wants to simulate for a specific number of + * instructions rather than ticks. + * + * @param tid Thread monitor. + * @param insts Number of instructions into the future. + * @param cause Cause to signal in the exit event. */ - virtual BranchPred *getBranchPred() { return NULL; }; + void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); - virtual Counter totalInstructions() const = 0; + /** + * Schedule an event that exits the simulation loops after a + * predefined number of load operations. + * + * This method is usually called from the configuration script to + * get an exit event some time in the future. It is typically used + * when the script wants to simulate for a specific number of + * loads rather than ticks. + * + * @param tid Thread monitor. + * @param loads Number of load instructions into the future. + * @param cause Cause to signal in the exit event. + */ + void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); // Function tracing private: @@ -354,13 +465,24 @@ class BaseCPU : public MemObject } static int numSimulatedCPUs() { return cpuList.size(); } - static Counter numSimulatedInstructions() + static Counter numSimulatedInsts() { Counter total = 0; int size = cpuList.size(); for (int i = 0; i < size; ++i) - total += cpuList[i]->totalInstructions(); + total += cpuList[i]->totalInsts(); + + return total; + } + + static Counter numSimulatedOps() + { + Counter total = 0; + + int size = cpuList.size(); + for (int i = 0; i < size; ++i) + total += cpuList[i]->totalOps(); return total; } @@ -372,4 +494,6 @@ class BaseCPU : public MemObject Stats::Scalar numWorkItemsCompleted; }; +#endif // THE_ISA == NULL_ISA + #endif // __CPU_BASE_HH__