X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fbase.hh;h=cd30d29bcaf31ebccf98143d9cdcd6a9439b88e5;hb=e09e9fa279dec86b171b5e3efeb7057fa0d21cc9;hp=41c79dff666130c7a04876d398e0e3301eb4864d;hpb=39f314cc151b0a05ee0e654d52bad1c906fac668;p=gem5.git diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 41c79dff6..cd30d29bc 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -58,17 +58,11 @@ #include "sim/full_system.hh" #include "sim/insttracer.hh" -class BaseCPUParams; +struct BaseCPUParams; class BranchPred; class CheckerCPU; class ThreadContext; class System; -class Port; - -namespace TheISA -{ - class Predecoder; -} class CPUProgressEvent : public Event { @@ -94,8 +88,7 @@ class CPUProgressEvent : public Event class BaseCPU : public MemObject { protected: - // CPU's clock period in terms of the number of ticks of curTime. - Tick clock; + // @todo remove me after debugging with legion done Tick instCnt; // every cpu has an id, put it in the base cpu @@ -104,6 +97,26 @@ class BaseCPU : public MemObject // therefore no setCpuId() method is provided int _cpuId; + /** instruction side request id that must be placed in all requests */ + MasterID _instMasterId; + + /** data side request id that must be placed in all requests */ + MasterID _dataMasterId; + + /** An intrenal representation of a task identifier within gem5. This is + * used so the CPU can add which taskId (which is an internal representation + * of the OS process ID) to each request so components in the memory system + * can track which process IDs are ultimately interacting with them + */ + uint32_t _taskId; + + /** The current OS process ID that is executing on this processor. This is + * used to generate a taskId */ + uint32_t _pid; + + /** Is the CPU switched out or active? */ + bool _switchedOut; + /** * Define a base class for the CPU ports (instruction and data) * that is refined in the subclasses. This class handles the @@ -112,7 +125,7 @@ class BaseCPU : public MemObject * both atomic and timing access is to panic and the corresponding * subclasses have to override these methods. */ - class CpuPort : public Port + class CpuPort : public MasterPort { public: @@ -123,51 +136,71 @@ class BaseCPU : public MemObject * @param _name structural owner of this port */ CpuPort(const std::string& _name, MemObject* _owner) : - Port(_name, _owner) + MasterPort(_name, _owner) { } protected: - virtual bool recvTiming(PacketPtr pkt); - - virtual Tick recvAtomic(PacketPtr pkt); + virtual bool recvTimingResp(PacketPtr pkt); virtual void recvRetry(); - void recvFunctional(PacketPtr pkt); - - void recvRangeChange(); + virtual void recvFunctionalSnoop(PacketPtr pkt); }; public: + + /** + * Purely virtual method that returns a reference to the data + * port. All subclasses must implement this method. + * + * @return a reference to the data port + */ + virtual CpuPort &getDataPort() = 0; + + /** + * Purely virtual method that returns a reference to the instruction + * port. All subclasses must implement this method. + * + * @return a reference to the instruction port + */ + virtual CpuPort &getInstPort() = 0; + /** Reads this CPU's ID. */ int cpuId() { return _cpuId; } -// Tick currentTick; - inline Tick frequency() const { return SimClock::Frequency / clock; } - inline Tick ticks(int numCycles) const { return clock * numCycles; } - inline Tick curCycle() const { return curTick() / clock; } - inline Tick tickToCycles(Tick val) const { return val / clock; } + /** Reads this CPU's unique data requestor ID */ + MasterID dataMasterId() { return _dataMasterId; } + /** Reads this CPU's unique instruction requestor ID */ + MasterID instMasterId() { return _instMasterId; } + + /** + * Get a master port on this CPU. All CPUs have a data and + * instruction port, and this method uses getDataPort and + * getInstPort of the subclasses to resolve the two ports. + * + * @param if_name the port name + * @param idx ignored index + * + * @return a reference to the port with the given name + */ + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); + + /** Get cpu task id */ + uint32_t taskId() const { return _taskId; } + /** Set cpu task id */ + void taskId(uint32_t id) { _taskId = id; } + + uint32_t getPid() const { return _pid; } + void setPid(uint32_t pid) { _pid = pid; } + inline void workItemBegin() { numWorkItemsStarted++; } inline void workItemEnd() { numWorkItemsCompleted++; } // @todo remove me after debugging with legion done Tick instCount() { return instCnt; } - /** The next cycle the CPU should be scheduled, given a cache - * access or quiesce event returning on this cycle. This function - * may return curTick() if the CPU should run on the current cycle. - */ - Tick nextCycle(); - - /** The next cycle the CPU should be scheduled, given a cache - * access or quiesce event returning on the given Tick. This - * function may return curTick() if the CPU should run on the - * current cycle. - * @param begin_tick The tick that the event is completing on. - */ - Tick nextCycle(Tick begin_tick); - TheISA::MicrocodeRom microcodeRom; protected: @@ -222,7 +255,6 @@ class BaseCPU : public MemObject protected: std::vector threadContexts; - std::vector predecoders; Trace::InstTracer * tracer; @@ -237,16 +269,16 @@ class BaseCPU : public MemObject /// Notify the CPU that the indicated context is now active. The /// delay parameter indicates the number of ticks to wait before /// executing (typically 0 or 1). - virtual void activateContext(int thread_num, int delay) {} + virtual void activateContext(ThreadID thread_num, Cycles delay) {} /// Notify the CPU that the indicated context is now suspended. - virtual void suspendContext(int thread_num) {} + virtual void suspendContext(ThreadID thread_num) {} /// Notify the CPU that the indicated context is now deallocated. - virtual void deallocateContext(int thread_num) {} + virtual void deallocateContext(ThreadID thread_num) {} /// Notify the CPU that the indicated context is now halted. - virtual void haltContext(int thread_num) {} + virtual void haltContext(ThreadID thread_num) {} /// Given a Thread Context pointer return the thread num int findContext(ThreadContext *tc); @@ -258,7 +290,7 @@ class BaseCPU : public MemObject typedef BaseCPUParams Params; const Params *params() const { return reinterpret_cast(_params); } - BaseCPU(Params *params); + BaseCPU(Params *params, bool is_checker = false); virtual ~BaseCPU(); virtual void init(); @@ -269,13 +301,45 @@ class BaseCPU : public MemObject void registerThreadContexts(); - /// Prepare for another CPU to take over execution. When it is - /// is ready (drained pipe) it signals the sampler. + /** + * Prepare for another CPU to take over execution. + * + * When this method exits, all internal state should have been + * flushed. After the method returns, the simulator calls + * takeOverFrom() on the new CPU with this CPU as its parameter. + */ virtual void switchOut(); - /// Take over execution from the given CPU. Used for warm-up and - /// sampling. - virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); + /** + * Load the state of a CPU from the previous CPU object, invoked + * on all new CPUs that are about to be switched in. + * + * A CPU model implementing this method is expected to initialize + * its state from the old CPU and connect its memory (unless they + * are already connected) to the memories connected to the old + * CPU. + * + * @param cpu CPU to initialize read state from. + */ + virtual void takeOverFrom(BaseCPU *cpu); + + /** + * Flush all TLBs in the CPU. + * + * This method is mainly used to flush stale translations when + * switching CPUs. It is also exported to the Python world to + * allow it to request a TLB flush after draining the CPU to make + * it easier to compare traces when debugging + * handover/checkpointing. + */ + void flushTLBs(); + + /** + * Determine if the CPU is switched out. + * + * @return True if the CPU is switched out, false otherwise. + */ + bool switchedOut() const { return _switchedOut; } /** * Number of threads we're actually simulating (<= SMT_MAX_THREADS). @@ -299,8 +363,6 @@ class BaseCPU : public MemObject System *system; - Tick phase; - /** * Serialize this object to the given output stream. * @param os The stream to serialize to. @@ -320,7 +382,9 @@ class BaseCPU : public MemObject */ virtual BranchPred *getBranchPred() { return NULL; }; - virtual Counter totalInstructions() const = 0; + virtual Counter totalInsts() const = 0; + + virtual Counter totalOps() const = 0; // Function tracing private: @@ -343,13 +407,24 @@ class BaseCPU : public MemObject } static int numSimulatedCPUs() { return cpuList.size(); } - static Counter numSimulatedInstructions() + static Counter numSimulatedInsts() + { + Counter total = 0; + + int size = cpuList.size(); + for (int i = 0; i < size; ++i) + total += cpuList[i]->totalInsts(); + + return total; + } + + static Counter numSimulatedOps() { Counter total = 0; int size = cpuList.size(); for (int i = 0; i < size; ++i) - total += cpuList[i]->totalInstructions(); + total += cpuList[i]->totalOps(); return total; }