X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fbase.hh;h=d4de55453dbd7e794294fc63b69c9ea199a9fe01;hb=af6aaf258171027af8d3cf0ef86dddff501a3ccb;hp=e0d2340e965b0dace373720f4d7513eb5036954a;hpb=641ee83e40bcb11b6fa1027c548ea11e7c4ce7ea;p=gem5.git diff --git a/src/cpu/base.hh b/src/cpu/base.hh index e0d2340e9..d4de55453 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -1,5 +1,18 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan + * Copyright (c) 2011 Regents of the University of California * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,6 +40,7 @@ * * Authors: Steve Reinhardt * Nathan Binkert + * Rick Strong */ #ifndef __CPU_BASE_HH__ @@ -35,16 +49,19 @@ #include #include "arch/isa_traits.hh" +#include "arch/microcode_rom.hh" #include "base/statistics.hh" #include "config/full_system.hh" +#include "config/the_isa.hh" +#include "mem/mem_object.hh" #include "sim/eventq.hh" #include "sim/insttracer.hh" -#include "mem/mem_object.hh" #if FULL_SYSTEM #include "arch/interrupts.hh" #endif +class BaseCPUParams; class BranchPred; class CheckerCPU; class ThreadContext; @@ -59,16 +76,22 @@ namespace TheISA class CPUProgressEvent : public Event { protected: - Tick interval; + Tick _interval; Counter lastNumInst; BaseCPU *cpu; + bool _repeatEvent; public: - CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); + CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); void process(); - virtual const char *description(); + void interval(Tick ival) { _interval = ival; } + Tick interval() { return _interval; } + + void repeatEvent(bool repeat) { _repeatEvent = repeat; } + + virtual const char *description() const; }; class BaseCPU : public MemObject @@ -78,53 +101,124 @@ class BaseCPU : public MemObject Tick clock; // @todo remove me after debugging with legion done Tick instCnt; + // every cpu has an id, put it in the base cpu + // Set at initialization, only time a cpuId might change is during a + // takeover (which should be done from within the BaseCPU anyway, + // therefore no setCpuId() method is provided + int _cpuId; + + /** + * Define a base class for the CPU ports (instruction and data) + * that is refined in the subclasses. This class handles the + * common cases, i.e. the functional accesses and the status + * changes and address range queries. The default behaviour for + * both atomic and timing access is to panic and the corresponding + * subclasses have to override these methods. + */ + class CpuPort : public Port + { + public: + + /** + * Create a CPU port with a name and a structural owner. + * + * @param _name port name including the owner + * @param _name structural owner of this port + */ + CpuPort(const std::string& _name, MemObject* _owner) : + Port(_name, _owner) + { } + + protected: + + virtual bool recvTiming(PacketPtr pkt); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvRetry(); + + void recvFunctional(PacketPtr pkt); + + void recvRangeChange(); + + }; public: + /** Reads this CPU's ID. */ + int cpuId() { return _cpuId; } + // Tick currentTick; - inline Tick frequency() const { return Clock::Frequency / clock; } + inline Tick frequency() const { return SimClock::Frequency / clock; } inline Tick ticks(int numCycles) const { return clock * numCycles; } - inline Tick curCycle() const { return curTick / clock; } + inline Tick curCycle() const { return curTick() / clock; } inline Tick tickToCycles(Tick val) const { return val / clock; } + inline void workItemBegin() { numWorkItemsStarted++; } + inline void workItemEnd() { numWorkItemsCompleted++; } // @todo remove me after debugging with legion done Tick instCount() { return instCnt; } /** The next cycle the CPU should be scheduled, given a cache * access or quiesce event returning on this cycle. This function - * may return curTick if the CPU should run on the current cycle. + * may return curTick() if the CPU should run on the current cycle. */ Tick nextCycle(); /** The next cycle the CPU should be scheduled, given a cache * access or quiesce event returning on the given Tick. This - * function may return curTick if the CPU should run on the + * function may return curTick() if the CPU should run on the * current cycle. * @param begin_tick The tick that the event is completing on. */ Tick nextCycle(Tick begin_tick); + TheISA::MicrocodeRom microcodeRom; + #if FULL_SYSTEM protected: -// uint64_t interrupts[TheISA::NumInterruptLevels]; -// uint64_t intstatus; - TheISA::Interrupts interrupts; + TheISA::Interrupts *interrupts; public: - virtual void post_interrupt(int int_num, int index); - virtual void clear_interrupt(int int_num, int index); - virtual void clear_interrupts(); - virtual uint64_t get_interrupts(int int_num); + TheISA::Interrupts * + getInterruptController() + { + return interrupts; + } - bool check_interrupts(ThreadContext * tc) const - { return interrupts.check_interrupts(tc); } + virtual void wakeup() = 0; + + void + postInterrupt(int int_num, int index) + { + interrupts->post(int_num, index); + wakeup(); + } + + void + clearInterrupt(int int_num, int index) + { + interrupts->clear(int_num, index); + } + + void + clearInterrupts() + { + interrupts->clearAll(); + } + + bool + checkInterrupts(ThreadContext *tc) const + { + return interrupts->checkInterrupts(tc); + } class ProfileEvent : public Event { private: BaseCPU *cpu; - int interval; + Tick interval; public: - ProfileEvent(BaseCPU *cpu, int interval); + ProfileEvent(BaseCPU *cpu, Tick interval); void process(); }; ProfileEvent *profileEvent; @@ -138,6 +232,9 @@ class BaseCPU : public MemObject public: + // Mask to align PCs to MachInst sized boundaries + static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); + /// Provide access to the tracer pointer Trace::InstTracer * getTracer() { return tracer; } @@ -162,40 +259,9 @@ class BaseCPU : public MemObject ThreadContext *getContext(int tn) { return threadContexts[tn]; } public: - struct Params - { - std::string name; - int numberOfThreads; - bool deferRegistration; - Counter max_insts_any_thread; - Counter max_insts_all_threads; - Counter max_loads_any_thread; - Counter max_loads_all_threads; - Tick clock; - bool functionTrace; - Tick functionTraceStart; - System *system; - int cpu_id; - Trace::InstTracer * tracer; - - Tick phase; -#if FULL_SYSTEM - Tick profile; - - bool do_statistics_insts; - bool do_checkpoint_insts; - bool do_quiesce; -#endif - Tick progress_interval; - BaseCPU *checker; - - TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core - - Params(); - }; - - const Params *params; - + typedef BaseCPUParams Params; + const Params *params() const + { return reinterpret_cast(_params); } BaseCPU(Params *params); virtual ~BaseCPU(); @@ -203,7 +269,7 @@ class BaseCPU : public MemObject virtual void startup(); virtual void regStats(); - virtual void activateWhenReady(int tid) {}; + virtual void activateWhenReady(ThreadID tid) {}; void registerThreadContexts(); @@ -219,7 +285,7 @@ class BaseCPU : public MemObject * Number of threads we're actually simulating (<= SMT_MAX_THREADS). * This is a constant for the duration of the simulation. */ - int number_of_threads; + ThreadID numThreads; /** * Vector of per-thread instruction-based event queues. Used for @@ -261,7 +327,7 @@ class BaseCPU : public MemObject */ virtual BranchPred *getBranchPred() { return NULL; }; - virtual Counter totalInstructions() const { return 0; } + virtual Counter totalInstructions() const = 0; // Function tracing private: @@ -273,17 +339,16 @@ class BaseCPU : public MemObject void enableFunctionTrace(); void traceFunctionsInternal(Addr pc); - protected: + private: + static std::vector cpuList; //!< Static global cpu list + + public: void traceFunctions(Addr pc) { if (functionTracingEnabled) traceFunctionsInternal(pc); } - private: - static std::vector cpuList; //!< Static global cpu list - - public: static int numSimulatedCPUs() { return cpuList.size(); } static Counter numSimulatedInstructions() { @@ -298,7 +363,9 @@ class BaseCPU : public MemObject public: // Number of CPU cycles simulated - Stats::Scalar<> numCycles; + Stats::Scalar numCycles; + Stats::Scalar numWorkItemsStarted; + Stats::Scalar numWorkItemsCompleted; }; #endif // __CPU_BASE_HH__