X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fchecker%2Fcpu.cc;h=229066fcc9b3be190e38260a26f12649dbce6164;hb=43335495754abac71377bbd6df0c668b60b22822;hp=b02c0701fe4248d7206d7f42241d14c34486481e;hpb=e3b19cb294c98466a431950888045c6b5d24b675;p=gem5.git

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b02c0701f..229066fcc 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -44,6 +44,7 @@
 #include <list>
 #include <string>
 
+#include "arch/generic/tlb.hh"
 #include "arch/kernel_stats.hh"
 #include "arch/vtophys.hh"
 #include "cpu/checker/cpu.hh"
@@ -53,7 +54,6 @@
 #include "cpu/thread_context.hh"
 #include "params/CheckerCPU.hh"
 #include "sim/full_system.hh"
-#include "sim/tlb.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -154,8 +154,8 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
 
     // Need to account for multiple accesses like the Atomic and TimingSimple
     while (1) {
-        memReq = new Request();
-        memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
+        memReq = new Request(0, addr, size, flags, masterId,
+                             thread->pcState().instAddr(), tc->contextId(), 0);
 
         // translate to physical address
         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
@@ -231,6 +231,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
     bool checked_flags = false;
     bool flags_match = true;
     Addr pAddr = 0x0;
+    static uint8_t zero_data[64] = {};
 
     int fullSize = size;
 
@@ -241,8 +242,8 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
 
     // Need to account for a multiple access like Atomic and Timing CPUs
     while (1) {
-        memReq = new Request();
-        memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
+        memReq = new Request(0, addr, size, flags, masterId,
+                             thread->pcState().instAddr(), tc->contextId(), 0);
 
         // translate to physical address
         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
@@ -298,16 +299,25 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
    // Cannot check this is actually what went to memory because
    // there stores can be in ld/st queue or coherent operations
    // overwriting values.
-   bool extraData;
+   bool extraData = false;
    if (unverifiedReq) {
        extraData = unverifiedReq->extraDataValid() ?
-                        unverifiedReq->getExtraData() : 1;
+                        unverifiedReq->getExtraData() : true;
+   }
+
+   // If the request is to ZERO a cache block, there is no data to check
+   // against, but it's all zero. We need something to compare to, so use a
+   // const set of zeros.
+   if (flags & Request::CACHE_BLOCK_ZERO) {
+       assert(!data);
+       assert(sizeof(zero_data) <= fullSize);
+       data = zero_data;
    }
 
    if (unverifiedReq && unverifiedMemData &&
        memcmp(data, unverifiedMemData, fullSize) && extraData) {
-           warn("%lli: Store value does not match value sent to memory!\
-                  data: %#x inst_data: %#x", curTick(), data,
+           warn("%lli: Store value does not match value sent to memory! "
+                  "data: %#x inst_data: %#x", curTick(), data,
                   unverifiedMemData);
        handleError();
    }