X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2FInOrderCPU.py;h=40af48b1922ff303ad08bf2a43160500db0274ea;hb=39f314cc151b0a05ee0e654d52bad1c906fac668;hp=d6db346d4bbd8467ad0c54579d93f8aaad55848c;hpb=4e00cc9900ec4f61899ee5be0c5b3827487e91f5;p=gem5.git

diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index d6db346d4..40af48b19 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -40,13 +40,13 @@ class InOrderCPU(BaseCPU):
     threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
     
     cachePorts = Param.Unsigned(2, "Cache Ports")
-    stageWidth = Param.Unsigned(1, "Stage width")
+    stageWidth = Param.Unsigned(4, "Stage width")
 
     fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from")
     dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
-    icache_port = Port("Instruction Port")
-    dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+
+    fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
+    memBlockSize = Param.Unsigned(64, "Memory Block Size")
 
     predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
@@ -69,8 +69,6 @@ class InOrderCPU(BaseCPU):
     functionTraceStart = Param.Tick(0, "Cycle to start function trace")
     stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
 
-    memBlockSize = Param.Unsigned(64, "Memory Block Size")
-
     multLatency = Param.Unsigned(1, "Latency for Multiply Operations")
     multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations")
     div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations")