X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fcpu.hh;h=1183f6fc9ab29876b2b80fd653a132c6978d5504;hb=7d0344704a9ecc566d82ad43ec44b4becbaf4d77;hp=6f189f8c97396a686773e3ab68d94622ea652d53;hpb=7aa423acad07f05ee547117406a72a5c1b4f6015;p=gem5.git

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 6f189f8c9..1183f6fc9 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -93,6 +93,7 @@ class InOrderCPU : public BaseCPU
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
+    typedef TheISA::CCReg CCReg;
     typedef TheISA::MiscReg MiscReg;
     typedef TheISA::RegIndex RegIndex;
 
@@ -327,6 +328,9 @@ class InOrderCPU : public BaseCPU
         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
     } floatRegs;
     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
+#ifdef ISA_HAS_CC_REGS
+    TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs];
+#endif
 
     /** ISA state */
     std::vector<TheISA::ISA *> isa;
@@ -334,9 +338,6 @@ class InOrderCPU : public BaseCPU
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 
-    /** Register Types Used in Dependency Tracking */
-    enum RegType { IntType, FloatType, MiscType, NumRegTypes};
-
     /** Global communication structure */
     TimeBuffer<TimeStruct> timeBuffer;
 
@@ -593,30 +594,17 @@ class InOrderCPU : public BaseCPU
 
     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 
+    CCReg readCCReg(RegIndex reg_idx, ThreadID tid);
+
     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 
     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 
     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 
-    RegType inline getRegType(RegIndex reg_idx)
-    {
-        switch (regIdxToClass(reg_idx)) {
-          case IntRegClass:
-            return IntType;
-
-          case FloatRegClass:
-            return FloatType;
-
-          case MiscRegClass:
-            return MiscType;
-
-          default:
-            panic("register %d out of range\n", reg_idx);
-        }
-    }
+    void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid);
 
-    RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
+    RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
 
     /** Reads a miscellaneous register. */
     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);