X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fcpu.hh;h=1183f6fc9ab29876b2b80fd653a132c6978d5504;hb=7d0344704a9ecc566d82ad43ec44b4becbaf4d77;hp=7ca4355de9e56291e88e0aad65369725785aaffb;hpb=1eec115c31395e2819c073a1859d75eb5933dac2;p=gem5.git

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 7ca4355de..1183f6fc9 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -65,6 +66,7 @@
 #include "cpu/o3/rename_map.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/timebuf.hh"
 #include "mem/packet.hh"
@@ -91,6 +93,7 @@ class InOrderCPU : public BaseCPU
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
+    typedef TheISA::CCReg CCReg;
     typedef TheISA::MiscReg MiscReg;
     typedef TheISA::RegIndex RegIndex;
 
@@ -112,10 +115,10 @@ class InOrderCPU : public BaseCPU
     void verifyMemoryMode() const;
 
     /** Return a reference to the data port. */
-    virtual CpuPort &getDataPort() { return dataPort; }
+    virtual MasterPort &getDataPort() { return dataPort; }
 
     /** Return a reference to the instruction port. */
-    virtual CpuPort &getInstPort() { return instPort; }
+    virtual MasterPort &getInstPort() { return instPort; }
 
     /** CPU ID */
     int cpu_id;
@@ -158,7 +161,7 @@ class InOrderCPU : public BaseCPU
      * CachePort class for the in-order CPU, interacting with a
      * specific CacheUnit in the pipeline.
      */
-    class CachePort : public CpuPort
+    class CachePort : public MasterPort
     {
 
       private:
@@ -325,6 +328,9 @@ class InOrderCPU : public BaseCPU
         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
     } floatRegs;
     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
+#ifdef ISA_HAS_CC_REGS
+    TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs];
+#endif
 
     /** ISA state */
     std::vector<TheISA::ISA *> isa;
@@ -332,9 +338,6 @@ class InOrderCPU : public BaseCPU
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 
-    /** Register Types Used in Dependency Tracking */
-    enum RegType { IntType, FloatType, MiscType, NumRegTypes};
-
     /** Global communication structure */
     TimeBuffer<TimeStruct> timeBuffer;
 
@@ -591,23 +594,17 @@ class InOrderCPU : public BaseCPU
 
     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 
+    CCReg readCCReg(RegIndex reg_idx, ThreadID tid);
+
     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 
     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 
     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 
-    RegType inline getRegType(RegIndex reg_idx)
-    {
-        if (reg_idx < TheISA::FP_Base_DepTag)
-            return IntType;
-        else if (reg_idx < TheISA::Ctrl_Base_DepTag)
-            return FloatType;
-        else
-            return MiscType;
-    }
+    void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid);
 
-    RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
+    RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
 
     /** Reads a miscellaneous register. */
     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);