X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fcpu.hh;h=1183f6fc9ab29876b2b80fd653a132c6978d5504;hb=7d0344704a9ecc566d82ad43ec44b4becbaf4d77;hp=7d22bc902815588fe2a487f6fd5727dbc753481d;hpb=c3d41a2def15cdaf2ac3984315f452dacc6a0884;p=gem5.git diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 7d22bc902..1183f6fc9 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -1,4 +1,17 @@ /* + * Copyright (c) 2012-2013 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2007 MIPS Technologies, Inc. * All rights reserved. * @@ -53,6 +66,7 @@ #include "cpu/o3/rename_map.hh" #include "cpu/activity.hh" #include "cpu/base.hh" +#include "cpu/reg_class.hh" #include "cpu/simple_thread.hh" #include "cpu/timebuf.hh" #include "mem/packet.hh" @@ -61,6 +75,7 @@ #include "sim/eventq.hh" #include "sim/process.hh" +class CacheUnit; class ThreadContext; class MemInterface; class MemObject; @@ -78,6 +93,7 @@ class InOrderCPU : public BaseCPU typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; typedef TheISA::MiscReg MiscReg; typedef TheISA::RegIndex RegIndex; @@ -96,6 +112,14 @@ class InOrderCPU : public BaseCPU /* Destructor */ ~InOrderCPU(); + void verifyMemoryMode() const; + + /** Return a reference to the data port. */ + virtual MasterPort &getDataPort() { return dataPort; } + + /** Return a reference to the instruction port. */ + virtual MasterPort &getInstPort() { return instPort; } + /** CPU ID */ int cpu_id; @@ -132,6 +156,34 @@ class InOrderCPU : public BaseCPU /** Overall CPU status. */ Status _status; private: + + /** + * CachePort class for the in-order CPU, interacting with a + * specific CacheUnit in the pipeline. + */ + class CachePort : public MasterPort + { + + private: + /** Pointer to cache unit */ + CacheUnit *cacheUnit; + + public: + /** Default constructor. */ + CachePort(CacheUnit *_cacheUnit, const std::string& name); + + protected: + + /** Timing version of receive */ + bool recvTimingResp(PacketPtr pkt); + + /** Handles doing a retry of a failed timing request. */ + void recvRetry(); + + /** Ignoring snoops for now. */ + void recvTimingSnoopReq(PacketPtr pkt) { } + }; + /** Define TickEvent for the CPU */ class TickEvent : public Event { @@ -147,17 +199,17 @@ class InOrderCPU : public BaseCPU void process(); /** Returns the description of the tick event. */ - const char *description(); + const char *description() const; }; /** The tick event used for scheduling CPU ticks. */ TickEvent tickEvent; /** Schedule tick event, regardless of its current state. */ - void scheduleTickEvent(int delay) + void scheduleTickEvent(Cycles delay) { assert(!tickEvent.scheduled() || tickEvent.squashed()); - reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true); + reschedule(&tickEvent, clockEdge(delay), true); } /** Unschedule tick event, regardless of its current state. */ @@ -229,10 +281,10 @@ class InOrderCPU : public BaseCPU void process(); /** Returns the description of the CPU event. */ - const char *description(); + const char *description() const; /** Schedule Event */ - void scheduleEvent(int delay); + void scheduleEvent(Cycles delay); /** Unschedule This Event */ void unscheduleEvent(); @@ -240,10 +292,14 @@ class InOrderCPU : public BaseCPU /** Schedule a CPU Event */ void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid, - DynInstPtr inst, unsigned delay = 0, + DynInstPtr inst, Cycles delay = Cycles(0), CPUEventPri event_pri = InOrderCPU_Pri); public: + + /** Width (processing bandwidth) of each stage */ + int stageWidth; + /** Interface between the CPU and CPU resources. */ ResourcePool *resPool; @@ -257,22 +313,9 @@ class InOrderCPU : public BaseCPU /** Used by resources to signify a denied access to a resource. */ ResourceRequest *dummyReq[ThePipeline::MaxThreads]; - /** Identifies the resource id that identifies a fetch - * access unit. - */ - unsigned fetchPortIdx; - - /** Identifies the resource id that identifies a data - * access unit. - */ - unsigned dataPortIdx; - /** The Pipeline Stages for the CPU */ PipelineStage *pipelineStage[ThePipeline::NumStages]; - /** Width (processing bandwidth) of each stage */ - int stageWidth; - /** Program Counters */ TheISA::PCState pc[ThePipeline::MaxThreads]; @@ -285,16 +328,16 @@ class InOrderCPU : public BaseCPU FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; } floatRegs; TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; +#ifdef ISA_HAS_CC_REGS + TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs]; +#endif /** ISA state */ - TheISA::ISA isa[ThePipeline::MaxThreads]; + std::vector isa; /** Dependency Tracker for Integer & Floating Point Regs */ RegDepMap archRegDepMap[ThePipeline::MaxThreads]; - /** Register Types Used in Dependency Tracking */ - enum RegType { IntType, FloatType, MiscType, NumRegTypes}; - /** Global communication structure */ TimeBuffer timeBuffer; @@ -304,7 +347,7 @@ class InOrderCPU : public BaseCPU TheISA::TLB *getITBPtr(); TheISA::TLB *getDTBPtr(); - Decoder *getDecoderPtr(); + TheISA::Decoder *getDecoderPtr(unsigned tid); /** Accessor Type for the SkedCache */ typedef uint32_t SkedID; @@ -396,6 +439,14 @@ class InOrderCPU : public BaseCPU } }; + private: + + /** Data port. Note that it has to appear after the resPool. */ + CachePort dataPort; + + /** Instruction port. Note that it has to appear after the resPool. */ + CachePort instPort; + public: /** Registers statistics. */ @@ -409,9 +460,6 @@ class InOrderCPU : public BaseCPU /** Initialize the CPU */ void init(); - /** Get a Memory Port */ - Port* getPort(const std::string &if_name, int idx = 0); - /** HW return from error interrupt. */ Fault hwrei(ThreadID tid); @@ -436,19 +484,20 @@ class InOrderCPU : public BaseCPU /** Schedule a syscall on the CPU */ void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, - int delay = 0); + Cycles delay = Cycles(0)); /** Executes a syscall.*/ void syscall(int64_t callnum, ThreadID tid); /** Schedule a trap on the CPU */ - void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0); + void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, + Cycles delay = Cycles(0)); /** Perform trap to Handle Given Fault */ void trap(Fault fault, ThreadID tid, DynInstPtr inst); /** Schedule thread activation on the CPU */ - void activateContext(ThreadID tid, int delay = 0); + void activateContext(ThreadID tid, Cycles delay = Cycles(0)); /** Add Thread to Active Threads List. */ void activateThread(ThreadID tid); @@ -457,25 +506,25 @@ class InOrderCPU : public BaseCPU void activateThreadInPipeline(ThreadID tid); /** Schedule Thread Activation from Ready List */ - void activateNextReadyContext(int delay = 0); + void activateNextReadyContext(Cycles delay = Cycles(0)); /** Add Thread From Ready List to Active Threads List. */ void activateNextReadyThread(); /** Schedule a thread deactivation on the CPU */ - void deactivateContext(ThreadID tid, int delay = 0); + void deactivateContext(ThreadID tid, Cycles delay = Cycles(0)); /** Remove from Active Thread List */ void deactivateThread(ThreadID tid); /** Schedule a thread suspension on the CPU */ - void suspendContext(ThreadID tid, int delay = 0); + void suspendContext(ThreadID tid); /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */ void suspendThread(ThreadID tid); /** Schedule a thread halt on the CPU */ - void haltContext(ThreadID tid, int delay = 0); + void haltContext(ThreadID tid); /** Halt Thread, Remove from Active Thread List, Place Thread on Halted * Threads List @@ -486,7 +535,8 @@ class InOrderCPU : public BaseCPU * squashDueToMemStall() - squashes pipeline * @note: maybe squashContext/squashThread would be better? */ - void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0); + void squashFromMemStall(DynInstPtr inst, ThreadID tid, + Cycles delay = Cycles(0)); void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid); void removePipelineStalls(ThreadID tid); @@ -544,23 +594,17 @@ class InOrderCPU : public BaseCPU FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid); + CCReg readCCReg(RegIndex reg_idx, ThreadID tid); + void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid); void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid); void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid); - RegType inline getRegType(RegIndex reg_idx) - { - if (reg_idx < TheISA::FP_Base_DepTag) - return IntType; - else if (reg_idx < TheISA::Ctrl_Base_DepTag) - return FloatType; - else - return MiscType; - } + void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid); - RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid); + RegIndex flattenRegIdx(RegIndex reg_idx, RegClass ®_type, ThreadID tid); /** Reads a miscellaneous register. */ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); @@ -765,7 +809,7 @@ class InOrderCPU : public BaseCPU } /** Count the Total Instructions Committed in the CPU. */ - virtual Counter totalInstructions() const + virtual Counter totalInsts() const { Counter total(0); @@ -775,6 +819,17 @@ class InOrderCPU : public BaseCPU return total; } + /** Count the Total Ops Committed in the CPU. */ + virtual Counter totalOps() const + { + Counter total(0); + + for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++) + total += thread[tid]->numOp; + + return total; + } + /** Pointer to the system. */ System *system; @@ -800,15 +855,6 @@ class InOrderCPU : public BaseCPU /** Pointers to all of the threads in the CPU. */ std::vector thread; - /** Pointer to the icache interface. */ - MemInterface *icacheInterface; - - /** Pointer to the dcache interface. */ - MemInterface *dcacheInterface; - - /** Whether or not the CPU should defer its registration. */ - bool deferRegistration; - /** Per-Stage Instruction Tracing */ bool stageTracing; @@ -855,6 +901,9 @@ class InOrderCPU : public BaseCPU /** Stat for the number of committed instructions per thread. */ Stats::Vector committedInsts; + /** Stat for the number of committed ops per thread. */ + Stats::Vector committedOps; + /** Stat for the number of committed instructions per thread. */ Stats::Vector smtCommittedInsts;