X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fcpu.hh;h=d8fe5c0573d44f0a8db00362bae2c14db47411cd;hb=b00949d88bb3185dfa2e27799de7f90e5a449be8;hp=4abcb05b417c22e7b544ec76b093f2456daaf2e4;hpb=ea8b347dc5d375572d8d19770024ec8be5fd5017;p=gem5.git

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 4abcb05b4..d8fe5c057 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -61,6 +73,7 @@
 #include "sim/eventq.hh"
 #include "sim/process.hh"
 
+class CacheUnit;
 class ThreadContext;
 class MemInterface;
 class MemObject;
@@ -96,6 +109,12 @@ class InOrderCPU : public BaseCPU
     /* Destructor */
     ~InOrderCPU();
     
+    /** Return a reference to the data port. */
+    virtual CpuPort &getDataPort() { return dataPort; }
+
+    /** Return a reference to the instruction port. */
+    virtual CpuPort &getInstPort() { return instPort; }
+
     /** CPU ID */
     int cpu_id;
 
@@ -132,6 +151,31 @@ class InOrderCPU : public BaseCPU
     /** Overall CPU status. */
     Status _status;
   private:
+
+    /**
+     * CachePort class for the in-order CPU, interacting with a
+     * specific CacheUnit in the pipeline.
+     */
+    class CachePort : public CpuPort
+    {
+
+      private:
+        /** Pointer to cache unit */
+        CacheUnit *cacheUnit;
+
+      public:
+        /** Default constructor. */
+        CachePort(CacheUnit *_cacheUnit);
+
+      protected:
+
+        /** Timing version of receive */
+        bool recvTiming(PacketPtr pkt);
+
+        /** Handles doing a retry of a failed timing request. */
+        void recvRetry();
+    };
+
     /** Define TickEvent for the CPU */
     class TickEvent : public Event
     {
@@ -244,6 +288,10 @@ class InOrderCPU : public BaseCPU
                           CPUEventPri event_pri = InOrderCPU_Pri);
 
   public:
+
+    /** Width (processing bandwidth) of each stage */
+    int stageWidth;
+
     /** Interface between the CPU and CPU resources. */
     ResourcePool *resPool;
 
@@ -257,22 +305,9 @@ class InOrderCPU : public BaseCPU
     /** Used by resources to signify a denied access to a resource. */
     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 
-    /** Identifies the resource id that identifies a fetch
-     * access unit.
-     */
-    unsigned fetchPortIdx;
-
-    /** Identifies the resource id that identifies a data
-     * access unit.
-     */
-    unsigned dataPortIdx;
-
     /** The Pipeline Stages for the CPU */
     PipelineStage *pipelineStage[ThePipeline::NumStages];
 
-    /** Width (processing bandwidth) of each stage */
-    int stageWidth;
-
     /** Program Counters */
     TheISA::PCState pc[ThePipeline::MaxThreads];
 
@@ -396,6 +431,14 @@ class InOrderCPU : public BaseCPU
         }
     };
 
+  private:
+
+    /** Data port. Note that it has to appear after the resPool. */
+    CachePort dataPort;
+
+    /** Instruction port. Note that it has to appear after the resPool. */
+    CachePort instPort;
+
   public:
 
     /** Registers statistics. */
@@ -409,9 +452,6 @@ class InOrderCPU : public BaseCPU
     /** Initialize the CPU */
     void init();
 
-    /** Get a Memory Port */
-    Port* getPort(const std::string &if_name, int idx = 0);
-
     /** HW return from error interrupt. */
     Fault hwrei(ThreadID tid);
 
@@ -765,7 +805,7 @@ class InOrderCPU : public BaseCPU
     }
 
     /** Count the Total Instructions Committed in the CPU. */
-    virtual Counter totalInstructions() const
+    virtual Counter totalInsts() const
     {
         Counter total(0);
 
@@ -775,6 +815,17 @@ class InOrderCPU : public BaseCPU
         return total;
     }
 
+    /** Count the Total Ops Committed in the CPU. */
+    virtual Counter totalOps() const
+    {
+        Counter total(0);
+
+        for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
+            total += thread[tid]->numOp;
+
+        return total;
+    }
+
     /** Pointer to the system. */
     System *system;
 
@@ -800,12 +851,6 @@ class InOrderCPU : public BaseCPU
     /** Pointers to all of the threads in the CPU. */
     std::vector<Thread *> thread;
 
-    /** Pointer to the icache interface. */
-    MemInterface *icacheInterface;
-
-    /** Pointer to the dcache interface. */
-    MemInterface *dcacheInterface;
-
     /** Whether or not the CPU should defer its registration. */
     bool deferRegistration;
 
@@ -855,6 +900,9 @@ class InOrderCPU : public BaseCPU
     /** Stat for the number of committed instructions per thread. */
     Stats::Vector committedInsts;
 
+    /** Stat for the number of committed ops per thread. */
+    Stats::Vector committedOps;
+
     /** Stat for the number of committed instructions per thread. */
     Stats::Vector smtCommittedInsts;