X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Finorder_dyn_inst.hh;h=f49476ec595c5d4763176918279bd8bdb12a4b5a;hb=e8e9f9731281e8c2ecb50a9aa318a65402cbee5c;hp=b374e24a6facaa901f6c516bd6d0c6d745bd7a12;hpb=71018f5e8b59c359065580a41a96f1a78a88dea9;p=gem5.git diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index b374e24a6..f49476ec5 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -71,7 +71,6 @@ */ // Forward declaration. -class StaticInstPtr; class ResourceRequest; class Packet; @@ -89,6 +88,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted // Floating point register type. typedef TheISA::FloatReg FloatReg; // Floating point register type. + typedef TheISA::FloatRegBits FloatRegBits; + // Floating point register type. typedef TheISA::MiscReg MiscReg; typedef short int PhysRegIndex; @@ -207,33 +208,38 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** How many source registers are ready. */ unsigned readyRegs; - /** An instruction src/dest has to be one of these types */ - union InstValue { - uint64_t integer; - double dbl; - }; - - //@TODO: Naming Convention for Enums? enum ResultType { None, Integer, Float, + FloatBits, Double }; + /** An instruction src/dest has to be one of these types */ + struct InstValue { + IntReg intVal; + union { + FloatReg f; + FloatRegBits i; + } fpVal; + + InstValue() + { + intVal = 0; + fpVal.i = 0; + } + }; /** Result of an instruction execution */ struct InstResult { ResultType type; - InstValue val; + InstValue res; Tick tick; InstResult() : type(None), tick(0) - { - val.integer = 0; - val.dbl = 0; - } + { } }; /** The source of the instruction; assumes for now that there's only one @@ -317,7 +323,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted std::string instName() { return (staticInst) ? staticInst->getName() : "undecoded-inst"; } - void setMachInst(ExtMachInst inst); + void setStaticInst(StaticInstPtr si); ExtMachInst getMachInst() { return staticInst->machInst; } @@ -349,6 +355,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Returns the fault type. */ Fault getFault() { return fault; } + /** Read this CPU's ID. */ + int cpuId(); + + /** Read this context's system-wide ID **/ + int contextId() { return thread->contextId(); } + //////////////////////////////////////////////////////////// // // INSTRUCTION TYPES - Forward checks to StaticInst object. @@ -385,6 +397,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted bool isQuiesce() const { return staticInst->isQuiesce(); } bool isIprAccess() const { return staticInst->isIprAccess(); } bool isUnverifiable() const { return staticInst->isUnverifiable(); } + bool isSyscall() const + { return staticInst->isSyscall(); } + ///////////////////////////////////////////// // @@ -464,12 +479,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted curSkedEntry++; if (inFrontEnd && curSkedEntry == frontSked_end) { - DPRINTF(InOrderDynInst, "[sn:%i] Switching to " + DPRINTF(InOrderDynInst, "[sn:%i] Switching to " "back end schedule.\n", seqNum); assert(backSked != NULL); - curSkedEntry.init(backSked); - curSkedEntry = backSked->begin(); - inFrontEnd = false; + curSkedEntry.init(backSked); + curSkedEntry = backSked->begin(); + inFrontEnd = false; } else if (!inFrontEnd && curSkedEntry == backSked_end) { return true; } @@ -509,10 +524,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted void trap(Fault fault); bool simPalCheck(int palFunc); #else - /** Calls a syscall. */ - void syscall(int64_t callnum); + short syscallNum; #endif + /** Emulates a syscall. */ + void syscall(int64_t callnum); + //////////////////////////////////////////////////////////// // // MULTITHREADING INTERFACE TO CPU MODELS @@ -594,32 +611,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted // MEMORY ACCESS // //////////////////////////////////////////// - /** - * Does a read to a given address. - * @param addr The address to read. - * @param data The read's data is written into this parameter. - * @param flags The request's flags. - * @return Returns any fault due to the read. - */ - template - Fault read(Addr addr, T &data, unsigned flags); - - Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); - - /** - * Does a write to a given address. - * @param data The data to be written. - * @param addr The address to write to. - * @param flags The request's flags. - * @param res The result of the write (for load locked/store conditionals). - * @return Returns any fault due to the write. - */ - template - Fault write(T data, Addr addr, unsigned flags, - uint64_t *res); - Fault writeBytes(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + + Fault writeMem(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res); /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory * Access Only valid for memory operations. @@ -847,10 +843,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted * source register to a value. */ void setIntSrc(int idx, uint64_t val); void setFloatSrc(int idx, FloatReg val); - void setFloatRegBitsSrc(int idx, uint64_t val); + void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val); - uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; } - uint64_t readIntSrc(int idx) { return instSrc[idx].integer; } + TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; } + uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; } /** These Instructions read a integer/float/misc. source register * value in the instruction. The instruction's execute function will @@ -872,20 +868,24 @@ class InOrderDynInst : public FastAlloc, public RefCounted return instResult[idx].type; } - uint64_t readIntResult(int idx) + IntReg readIntResult(int idx) + { + return instResult[idx].res.intVal; + } + + FloatReg readFloatResult(int idx) { - return instResult[idx].val.integer; + return instResult[idx].res.fpVal.f; } - /** Depending on type, return Float or Double */ - double readFloatResult(int idx) + FloatRegBits readFloatBitsResult(int idx) { - return instResult[idx].val.dbl; + return instResult[idx].res.fpVal.i; } Tick readResultTime(int idx) { return instResult[idx].tick; } - uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; } + IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; } /** This is the interface that an instruction will use to write * it's destination register. @@ -905,6 +905,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted virtual void setRegOtherThread(unsigned idx, const uint64_t &val, ThreadID tid = InvalidThreadID); + /** Returns the number of consecutive store conditional failures. */ + unsigned readStCondFailures() + { return thread->storeCondFailures; } + /** Sets the number of consecutive store conditional failures. */ void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; } @@ -917,6 +921,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Sets this instruction as entered on the CPU Reg Dep Map */ void setRegDepEntry() { status.set(RegDepMapEntry); } + /** Unsets this instruction as entered on the CPU Reg Dep Map */ + void clearRegDepEntry() { status.reset(RegDepMapEntry); } + /** Returns whether or not the entry is on the CPU Reg Dep Map */ bool isRegDepEntry() const { return status[RegDepMapEntry]; }