X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fpipeline_stage.hh;h=963d96afb539b7f30bce6850a39c31b5914ac740;hb=39f314cc151b0a05ee0e654d52bad1c906fac668;hp=be3a1093caa3ec838d6a43f1fd9ec3d1e6d13c51;hpb=ffa9ecb1fa71f1fe89a65975b2c558e312bbfbc8;p=gem5.git diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh index be3a1093c..963d96afb 100644 --- a/src/cpu/inorder/pipeline_stage.hh +++ b/src/cpu/inorder/pipeline_stage.hh @@ -36,11 +36,11 @@ #include #include "base/statistics.hh" -#include "base/timebuf.hh" -#include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/comm.hh" -#include "params/InOrderCPU.hh" +#include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_traits.hh" +#include "cpu/timebuf.hh" +#include "params/InOrderCPU.hh" class InOrderCPU; @@ -91,10 +91,7 @@ class PipelineStage public: PipelineStage(Params *params, unsigned stage_num); - /** MUST use init() function if this constructor is used. */ - PipelineStage() { } - - virtual ~PipelineStage() { } + virtual ~PipelineStage(); /** PipelineStage initialization. */ void init(Params *params); @@ -106,9 +103,7 @@ class PipelineStage void regStats(); /** Sets CPU pointer. */ - virtual void setCPU(InOrderCPU *cpu_ptr); - - virtual void scheduleStageStart(int delay, ThreadID tid) { } + void setCPU(InOrderCPU *cpu_ptr); /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer *tb_ptr); @@ -145,7 +140,7 @@ class PipelineStage /** Ticks stage, processing all input signals and executing as many * instructions as possible. */ - virtual void tick(); + void tick(); /** Set a resource stall in the pipeline-stage */ void setResStall(ResReqPtr res_req, ThreadID tid); @@ -154,7 +149,7 @@ class PipelineStage void unsetResStall(ResReqPtr res_req, ThreadID tid); /** Remove all stall signals for a particular thread; */ - virtual void removeStalls(ThreadID tid); + void removeStalls(ThreadID tid); /** Is there room in the stage buffer? */ int stageBufferAvail(); @@ -168,7 +163,7 @@ class PipelineStage * change (ie switching from from blocking to unblocking). * @param tid Thread id to stage instructions from. */ - virtual void processThread(bool &status_change, ThreadID tid); + void processThread(bool &status_change, ThreadID tid); /** Processes instructions from fetch and passes them on to rename. * Decoding of instructions actually happens when they are created in @@ -178,18 +173,13 @@ class PipelineStage virtual void processInsts(ThreadID tid); /** Process all resources on an instruction's resource schedule */ - virtual bool processInstSchedule(DynInstPtr inst, int &reqs_processed); + bool processInstSchedule(DynInstPtr inst, int &reqs_processed); /** Is there room in the next stage buffer for this instruction? */ - virtual bool canSendInstToStage(unsigned stage_num); + bool canSendInstToStage(unsigned stage_num); /** Send an instruction to the next stage buffer */ - virtual bool sendInstToNextStage(DynInstPtr inst); - - /** Inserts a thread's instructions into the skid buffer, to be staged - * once stage unblocks. - */ - virtual void skidInsert(ThreadID tid); + bool sendInstToNextStage(DynInstPtr inst); /** Total size of all skid buffers */ int skidSize(); @@ -198,7 +188,7 @@ class PipelineStage bool skidsEmpty(); /** Updates overall stage status based on all of the threads' statuses. */ - virtual void updateStatus(); + void updateStatus(); /** Separates instructions from fetch into individual lists of instructions * sorted by thread. @@ -206,13 +196,13 @@ class PipelineStage void sortInsts(); /** Reads all stall signals from the backwards communication timebuffer. */ - virtual void readStallSignals(ThreadID tid); + void readStallSignals(ThreadID tid); /** Checks all input signals and updates stage's status appropriately. */ - virtual bool checkSignalsAndUpdate(ThreadID tid); + bool checkSignalsAndUpdate(ThreadID tid); /** Checks all stall signals, and returns if any are true. */ - virtual bool checkStall(ThreadID tid) const; + bool checkStall(ThreadID tid) const; /** Returns if there any instructions from the previous stage * on this cycle. @@ -223,7 +213,7 @@ class PipelineStage * become blocked. * @return Returns true if there is a status change. */ - virtual bool block(ThreadID tid); + bool block(ThreadID tid); void blockDueToBuffer(ThreadID tid); @@ -231,27 +221,23 @@ class PipelineStage * signals back that stage has unblocked. * @return Returns true if there is a status change. */ - virtual bool unblock(ThreadID tid); + bool unblock(ThreadID tid); public: - virtual void activateThread(ThreadID tid); + void activateThread(ThreadID tid); - /** Squashes if there is a PC-relative branch that was predicted - * incorrectly. Sends squash information back to fetch. - */ - virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid); + /** Setup Squashing Information to be passed back thru the pipeline */ + void setupSquash(DynInstPtr inst, ThreadID tid); virtual void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid); - /** Squash instructions from stage buffer */ - virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid); - - /** Squashes due to commit signalling a squash. Changes status to - * squashing and clears block/unblock signals as needed. - */ + /** Perform squash of instructions above seq_num */ virtual void squash(InstSeqNum squash_num, ThreadID tid); + /** Squash instructions from stage buffer */ + void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid); + void dumpInsts(); protected: @@ -275,18 +261,8 @@ class PipelineStage */ unsigned instsProcessed; - /** Queue of all instructions coming from previous stage on this cycle. */ - std::queue insts[ThePipeline::MaxThreads]; - - /** Queue of instructions that are finished processing and ready to go - * next stage. This is used to prevent from processing an instrution more - * than once on any stage. NOTE: It is up to the PROGRAMMER must manage - * this as a queue - */ - std::list instsToNextStage; - /** Skid buffer between previous stage and this one. */ - std::queue skidBuffer[ThePipeline::MaxThreads]; + std::list skidBuffer[ThePipeline::MaxThreads]; /** Instruction used to signify that there is no *real* instruction in * buffer slot */ @@ -295,15 +271,15 @@ class PipelineStage /** SeqNum of Squashing Branch Delay Instruction (used for MIPS) */ Addr bdelayDoneSeqNum[ThePipeline::MaxThreads]; - /** Instruction used for squashing branch (used for MIPS) */ - DynInstPtr squashInst[ThePipeline::MaxThreads]; - /** Tells when their is a pending delay slot inst. to send * to rename. If there is, then wait squash after the next * instruction (used for MIPS). */ bool squashAfterDelaySlot[ThePipeline::MaxThreads]; + /** Instruction used for squashing branch (used for MIPS) */ + DynInstPtr squashInst[ThePipeline::MaxThreads]; + /** Maximum size of the inter-stage buffer connecting the previous stage to * this stage (which we call a skid buffer) */ unsigned stageBufferMax; @@ -347,6 +323,8 @@ class PipelineStage /** Is Next Stage Valid? */ bool nextStageValid; + bool idle; + /** Source of possible stalls. */ struct Stalls { bool stage[ThePipeline::NumStages];