X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fpipeline_stage.hh;h=963d96afb539b7f30bce6850a39c31b5914ac740;hb=39f314cc151b0a05ee0e654d52bad1c906fac668;hp=c971e400e6952df63f0096b7b51715e36385eb21;hpb=71b67d408bb595471a57dbe8e40cf5ac82c5d3b7;p=gem5.git diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh index c971e400e..963d96afb 100644 --- a/src/cpu/inorder/pipeline_stage.hh +++ b/src/cpu/inorder/pipeline_stage.hh @@ -36,11 +36,11 @@ #include #include "base/statistics.hh" -#include "base/timebuf.hh" -#include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/comm.hh" -#include "params/InOrderCPU.hh" +#include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_traits.hh" +#include "cpu/timebuf.hh" +#include "params/InOrderCPU.hh" class InOrderCPU; @@ -91,10 +91,7 @@ class PipelineStage public: PipelineStage(Params *params, unsigned stage_num); - /** MUST use init() function if this constructor is used. */ - PipelineStage() { } - - virtual ~PipelineStage() { } + virtual ~PipelineStage(); /** PipelineStage initialization. */ void init(Params *params); @@ -184,11 +181,6 @@ class PipelineStage /** Send an instruction to the next stage buffer */ bool sendInstToNextStage(DynInstPtr inst); - /** Inserts a thread's instructions into the skid buffer, to be staged - * once stage unblocks. - */ - virtual void skidInsert(ThreadID tid); - /** Total size of all skid buffers */ int skidSize(); @@ -235,21 +227,17 @@ class PipelineStage public: void activateThread(ThreadID tid); - /** Squashes if there is a PC-relative branch that was predicted - * incorrectly. Sends squash information back to fetch. - */ - void squashDueToBranch(DynInstPtr &inst, ThreadID tid); + /** Setup Squashing Information to be passed back thru the pipeline */ + void setupSquash(DynInstPtr inst, ThreadID tid); virtual void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid); + /** Perform squash of instructions above seq_num */ + virtual void squash(InstSeqNum squash_num, ThreadID tid); + /** Squash instructions from stage buffer */ void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid); - /** Squashes due to commit signalling a squash. Changes status to - * squashing and clears block/unblock signals as needed. - */ - virtual void squash(InstSeqNum squash_num, ThreadID tid); - void dumpInsts(); protected: @@ -273,18 +261,8 @@ class PipelineStage */ unsigned instsProcessed; - /** Queue of all instructions coming from previous stage on this cycle. */ - std::queue insts[ThePipeline::MaxThreads]; - - /** Queue of instructions that are finished processing and ready to go - * next stage. This is used to prevent from processing an instrution more - * than once on any stage. NOTE: It is up to the PROGRAMMER must manage - * this as a queue - */ - std::list instsToNextStage; - /** Skid buffer between previous stage and this one. */ - std::queue skidBuffer[ThePipeline::MaxThreads]; + std::list skidBuffer[ThePipeline::MaxThreads]; /** Instruction used to signify that there is no *real* instruction in * buffer slot */ @@ -293,15 +271,15 @@ class PipelineStage /** SeqNum of Squashing Branch Delay Instruction (used for MIPS) */ Addr bdelayDoneSeqNum[ThePipeline::MaxThreads]; - /** Instruction used for squashing branch (used for MIPS) */ - DynInstPtr squashInst[ThePipeline::MaxThreads]; - /** Tells when their is a pending delay slot inst. to send * to rename. If there is, then wait squash after the next * instruction (used for MIPS). */ bool squashAfterDelaySlot[ThePipeline::MaxThreads]; + /** Instruction used for squashing branch (used for MIPS) */ + DynInstPtr squashInst[ThePipeline::MaxThreads]; + /** Maximum size of the inter-stage buffer connecting the previous stage to * this stage (which we call a skid buffer) */ unsigned stageBufferMax;