X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fthread_context.hh;h=b1a3610275681511b7293f1e4b324fed93834da3;hb=7d0344704a9ecc566d82ad43ec44b4becbaf4d77;hp=2fb2ed85fd43b145698824efc4322bc569800096;hpb=d080581db1f9ee4e1e6d07d2b01c13c67908a391;p=gem5.git diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 2fb2ed85f..b1a361027 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -1,4 +1,17 @@ /* + * Copyright (c) 2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2007 MIPS Technologies, Inc. * All rights reserved. * @@ -32,12 +45,18 @@ #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__ #define __CPU_INORDER_THREAD_CONTEXT_HH__ +#include "config/the_isa.hh" +#include "cpu/inorder/cpu.hh" +#include "cpu/inorder/thread_state.hh" #include "cpu/exetrace.hh" #include "cpu/thread_context.hh" -#include "cpu/inorder/thread_state.hh" -#include "cpu/inorder/cpu.hh" +#include "arch/kernel_stats.hh" -class TranslatingPort; +class EndQuiesceEvent; +class CheckerCPU; +namespace Kernel { + class Statistics; +}; /** * Derived ThreadContext class for use with the InOrderCPU. It @@ -57,173 +76,219 @@ class InOrderThreadContext : public ThreadContext public: InOrderThreadContext() { } - /** Pointer to the CPU. */ + /** Pointer to the CPU. */ InOrderCPU *cpu; /** Pointer to the thread state that this TC corrseponds to. */ InOrderThreadState *thread; - /** Returns a pointer to the ITB. */ - TheISA::ITB *getITBPtr() { return cpu->itb; } + /** @TODO: PERF: Should we bind this to a pointer in constructor? */ + TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); } /** Returns a pointer to the DTB. */ - TheISA::DTB *getDTBPtr() { return cpu->dtb; } + /** @TODO: PERF: Should we bind this to a pointer in constructor? */ + TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); } + + /** Currently InOrder model does not support CheckerCPU, this is + * merely here for supporting compilation of gem5 with the Checker + * as a runtime option + */ + CheckerCPU *getCheckerCpuPtr() { return NULL; } + + TheISA::Decoder * + getDecoderPtr() + { + return cpu->getDecoderPtr(thread->contextId()); + } System *getSystemPtr() { return cpu->system; } /** Returns a pointer to this CPU. */ - virtual BaseCPU *getCpuPtr() { return cpu; } + BaseCPU *getCpuPtr() { return cpu; } /** Returns a pointer to this CPU. */ - virtual std::string getCpuName() { return cpu->name(); } + std::string getCpuName() { return cpu->name(); } /** Reads this CPU's ID. */ - virtual int cpuId() { return cpu->cpuId(); } + int cpuId() { return cpu->cpuId(); } - virtual int contextId() { return thread->contextId(); } + int contextId() { return thread->contextId(); } - virtual void setContextId(int id) { thread->setContextId(id); } + void setContextId(int id) { thread->setContextId(id); } /** Returns this thread's ID number. */ - virtual int threadId() { return thread->threadId(); } - virtual void setThreadId(int id) { return thread->setThreadId(id); } + int threadId() { return thread->threadId(); } + void setThreadId(int id) { return thread->setThreadId(id); } - virtual uint64_t readMicroPC() + uint64_t readMicroPC() { return 0; } - virtual void setMicroPC(uint64_t val) { }; + void setMicroPC(uint64_t val) { }; - virtual uint64_t readNextMicroPC() + uint64_t readNextMicroPC() { return 0; } - virtual void setNextMicroPC(uint64_t val) { }; + void setNextMicroPC(uint64_t val) { }; + + /** Returns a pointer to this thread's kernel statistics. */ + TheISA::Kernel::Statistics *getKernelStats() + { return thread->kernelStats; } + + PortProxy &getPhysProxy() { return thread->getPhysProxy(); } + + FSTranslatingPortProxy &getVirtProxy(); + + void initMemProxies(ThreadContext *tc) + { thread->initMemProxies(tc); } + + /** Dumps the function profiling information. + * @todo: Implement. + */ + void dumpFuncProfile(); + + /** Reads the last tick that this thread was activated on. */ + Tick readLastActivate(); + /** Reads the last tick that this thread was suspended on. */ + Tick readLastSuspend(); + + /** Clears the function profiling information. */ + void profileClear(); - virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } + /** Samples the function profiling information. */ + void profileSample(); + + /** Returns pointer to the quiesce event. */ + EndQuiesceEvent *getQuiesceEvent() + { + return this->thread->quiesceEvent; + } + + SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); } /** Returns a pointer to this thread's process. */ - virtual Process *getProcessPtr() { return thread->getProcessPtr(); } + Process *getProcessPtr() { return thread->getProcessPtr(); } /** Returns this thread's status. */ - virtual Status status() const { return thread->status(); } + Status status() const { return thread->status(); } /** Sets this thread's status. */ - virtual void setStatus(Status new_status) + void setStatus(Status new_status) { thread->setStatus(new_status); } /** Set the status to Active. Optional delay indicates number of * cycles to wait before beginning execution. */ - virtual void activate(int delay = 1); + void activate(Cycles delay = Cycles(1)); /** Set the status to Suspended. */ - virtual void suspend(int delay = 0); - - /** Set the status to Unallocated. */ - virtual void deallocate(int delay = 1); + void suspend(Cycles delay = Cycles(0)); /** Set the status to Halted. */ - virtual void halt(int delay = 0); + void halt(Cycles delay = Cycles(0)); /** Takes over execution of a thread from another CPU. */ - virtual void takeOverFrom(ThreadContext *old_context); + void takeOverFrom(ThreadContext *old_context); /** Registers statistics associated with this TC. */ - virtual void regStats(const std::string &name); - - /** Serializes state. */ - virtual void serialize(std::ostream &os); - - /** Unserializes state. */ - virtual void unserialize(Checkpoint *cp, const std::string §ion); + void regStats(const std::string &name); /** Returns this thread's ID number. */ - virtual int getThreadNum() { return thread->readTid(); } - - /** Returns the instruction this thread is currently committing. - * Only used when an instruction faults. - */ - virtual TheISA::MachInst getInst(); + int getThreadNum() { return thread->threadId(); } /** Copies the architectural registers from another TC into this TC. */ - virtual void copyArchRegs(ThreadContext *src_tc); + void copyArchRegs(ThreadContext *src_tc); /** Resets all architectural registers to 0. */ - virtual void clearArchRegs(); + void clearArchRegs(); /** Reads an integer register. */ - virtual uint64_t readIntReg(int reg_idx); + uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); + FloatReg readFloatReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx); + FloatRegBits readFloatRegBits(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); + CCReg readCCReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx); - - virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid); + uint64_t readRegOtherThread(int misc_reg, ThreadID tid); /** Sets an integer register to a value. */ - virtual void setIntReg(int reg_idx, uint64_t val); - - virtual void setFloatReg(int reg_idx, FloatReg val, int width); + void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val); + void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); + void setFloatRegBits(int reg_idx, FloatRegBits val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); + void setCCReg(int reg_idx, CCReg val); - virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid); + void setRegOtherThread(int misc_reg, + const MiscReg &val, + ThreadID tid); /** Reads this thread's PC. */ - virtual uint64_t readPC() - { return cpu->readPC(thread->readTid()); } + TheISA::PCState pcState() + { return cpu->pcState(thread->threadId()); } /** Sets this thread's PC. */ - virtual void setPC(uint64_t val); + void pcState(const TheISA::PCState &val) + { cpu->pcState(val, thread->threadId()); } - /** Reads this thread's next PC. */ - virtual uint64_t readNextPC() - { return cpu->readNextPC(thread->readTid()); } + /** Needs to be implemented for future CheckerCPU support. + * See O3CPU for examples on how to integrate Checker. + */ + void pcStateNoRecord(const TheISA::PCState &val) + {} - /** Sets this thread's next PC. */ - virtual void setNextPC(uint64_t val); + Addr instAddr() + { return cpu->instAddr(thread->threadId()); } - virtual uint64_t readNextNPC() - { return cpu->readNextNPC(thread->readTid()); } + Addr nextInstAddr() + { return cpu->nextInstAddr(thread->threadId()); } - virtual void setNextNPC(uint64_t val); + MicroPC microPC() + { return cpu->microPC(thread->threadId()); } /** Reads a miscellaneous register. */ - virtual MiscReg readMiscRegNoEffect(int misc_reg) - { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } + MiscReg readMiscRegNoEffect(int misc_reg) + { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscReg(int misc_reg) - { return cpu->readMiscReg(misc_reg, thread->readTid()); } + MiscReg readMiscReg(int misc_reg) + { return cpu->readMiscReg(misc_reg, thread->threadId()); } /** Sets a misc. register. */ - virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual void setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); + + int flattenIntIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); } + + int flattenFloatIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); } + + int flattenCCIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); } + + int flattenMiscIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); } - virtual void activateContext(int delay) - { cpu->activateContext(thread->readTid(), delay); } + void activateContext(Cycles delay) + { cpu->activateContext(thread->threadId(), delay); } - virtual void deallocateContext() - { cpu->deallocateContext(thread->readTid()); } + void deallocateContext() + { cpu->deallocateContext(thread->threadId()); } /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. - virtual unsigned readStCondFailures() + unsigned readStCondFailures() { return thread->storeCondFailures; } /** Sets the number of consecutive store conditional failures. */ - virtual void setStCondFailures(unsigned sc_failures) + void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; } // Only really makes sense for old CPU model. Lots of code @@ -232,44 +297,30 @@ class InOrderThreadContext : public ThreadContext /** Checks if the thread is misspeculating. Because it is * very difficult to determine if the thread is * misspeculating, this is set as false. */ - virtual bool misspeculating() { return false; } + bool misspeculating() { return false; } /** Executes a syscall in SE mode. */ - virtual void syscall(int64_t callnum) - { return cpu->syscall(callnum, thread->readTid()); } + void syscall(int64_t callnum) + { return cpu->syscall(callnum, thread->threadId()); } /** Reads the funcExeInst counter. */ - virtual Counter readFuncExeInst() { return thread->funcExeInst; } + Counter readFuncExeInst() { return thread->funcExeInst; } - virtual void changeRegFileContext(unsigned param, + void changeRegFileContext(unsigned param, unsigned val) { panic("Not supported!"); } - /** This function exits the thread context in the CPU and returns - * 1 if the CPU has no more active threads (meaning it's OK to exit); - * Used in syscall-emulation mode when a thread executes the 'exit' - * syscall. - */ - virtual int exit() - { - this->deallocate(); - - // If there are still threads executing in the system (for now - // this single cpu) - if (this->cpu->numActiveThreads() - 1 > 0) - return 0; // don't exit simulation - else - return 1; // exit simulation - } + uint64_t readIntRegFlat(int idx); + void setIntRegFlat(int idx, uint64_t val); - virtual void setThreadRescheduleCondition(uint64_t cond) - { - this->deallocate(); + FloatReg readFloatRegFlat(int idx); + void setFloatRegFlat(int idx, FloatReg val); - this->setStatus(ThreadContext::Suspended); + FloatRegBits readFloatRegBitsFlat(int idx); + void setFloatRegBitsFlat(int idx, FloatRegBits val); - activateContext(cond); - } + CCReg readCCRegFlat(int idx); + void setCCRegFlat(int idx, CCReg val); }; #endif