X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Finorder%2Fthread_context.hh;h=b1a3610275681511b7293f1e4b324fed93834da3;hb=7d0344704a9ecc566d82ad43ec44b4becbaf4d77;hp=3ed2e7f50fcc01a9f4915b79d6b31687aad80717;hpb=71b67d408bb595471a57dbe8e40cf5ac82c5d3b7;p=gem5.git diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 3ed2e7f50..b1a361027 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -1,4 +1,17 @@ /* + * Copyright (c) 2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2007 MIPS Technologies, Inc. * All rights reserved. * @@ -33,12 +46,17 @@ #define __CPU_INORDER_THREAD_CONTEXT_HH__ #include "config/the_isa.hh" +#include "cpu/inorder/cpu.hh" +#include "cpu/inorder/thread_state.hh" #include "cpu/exetrace.hh" #include "cpu/thread_context.hh" -#include "cpu/inorder/thread_state.hh" -#include "cpu/inorder/cpu.hh" +#include "arch/kernel_stats.hh" -class TranslatingPort; +class EndQuiesceEvent; +class CheckerCPU; +namespace Kernel { + class Statistics; +}; /** * Derived ThreadContext class for use with the InOrderCPU. It @@ -72,6 +90,18 @@ class InOrderThreadContext : public ThreadContext /** @TODO: PERF: Should we bind this to a pointer in constructor? */ TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); } + /** Currently InOrder model does not support CheckerCPU, this is + * merely here for supporting compilation of gem5 with the Checker + * as a runtime option + */ + CheckerCPU *getCheckerCpuPtr() { return NULL; } + + TheISA::Decoder * + getDecoderPtr() + { + return cpu->getDecoderPtr(thread->contextId()); + } + System *getSystemPtr() { return cpu->system; } /** Returns a pointer to this CPU. */ @@ -101,21 +131,16 @@ class InOrderThreadContext : public ThreadContext void setNextMicroPC(uint64_t val) { }; -#if FULL_SYSTEM - /** Returns a pointer to physical memory. */ - PhysicalMemory *getPhysMemPtr() - { assert(0); return 0; /*return cpu->physmem;*/ } - /** Returns a pointer to this thread's kernel statistics. */ TheISA::Kernel::Statistics *getKernelStats() { return thread->kernelStats; } - FunctionalPort *getPhysPort() { return thread->getPhysPort(); } + PortProxy &getPhysProxy() { return thread->getPhysProxy(); } - VirtualPort *getVirtPort(); + FSTranslatingPortProxy &getVirtProxy(); - void connectMemPorts(ThreadContext *tc) - { thread->connectMemPorts(tc); } + void initMemProxies(ThreadContext *tc) + { thread->initMemProxies(tc); } /** Dumps the function profiling information. * @todo: Implement. @@ -138,12 +163,11 @@ class InOrderThreadContext : public ThreadContext { return this->thread->quiesceEvent; } -#else - TranslatingPort *getMemPort() { return thread->getMemPort(); } + + SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); } /** Returns a pointer to this thread's process. */ Process *getProcessPtr() { return thread->getProcessPtr(); } -#endif /** Returns this thread's status. */ Status status() const { return thread->status(); } @@ -154,13 +178,13 @@ class InOrderThreadContext : public ThreadContext /** Set the status to Active. Optional delay indicates number of * cycles to wait before beginning execution. */ - void activate(int delay = 1); + void activate(Cycles delay = Cycles(1)); /** Set the status to Suspended. */ - void suspend(int delay = 0); + void suspend(Cycles delay = Cycles(0)); /** Set the status to Halted. */ - void halt(int delay = 0); + void halt(Cycles delay = Cycles(0)); /** Takes over execution of a thread from another CPU. */ void takeOverFrom(ThreadContext *old_context); @@ -168,19 +192,8 @@ class InOrderThreadContext : public ThreadContext /** Registers statistics associated with this TC. */ void regStats(const std::string &name); - /** Serializes state. */ - void serialize(std::ostream &os); - - /** Unserializes state. */ - void unserialize(Checkpoint *cp, const std::string §ion); - /** Returns this thread's ID number. */ - int getThreadNum() { return thread->readTid(); } - - /** Returns the instruction this thread is currently committing. - * Only used when an instruction faults. - */ - TheISA::MachInst getInst(); + int getThreadNum() { return thread->threadId(); } /** Copies the architectural registers from another TC into this TC. */ void copyArchRegs(ThreadContext *src_tc); @@ -195,6 +208,8 @@ class InOrderThreadContext : public ThreadContext FloatRegBits readFloatRegBits(int reg_idx); + CCReg readCCReg(int reg_idx); + uint64_t readRegOtherThread(int misc_reg, ThreadID tid); /** Sets an integer register to a value. */ @@ -204,37 +219,43 @@ class InOrderThreadContext : public ThreadContext void setFloatRegBits(int reg_idx, FloatRegBits val); + void setCCReg(int reg_idx, CCReg val); + void setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid); /** Reads this thread's PC. */ - uint64_t readPC() - { return cpu->readPC(thread->readTid()); } + TheISA::PCState pcState() + { return cpu->pcState(thread->threadId()); } /** Sets this thread's PC. */ - void setPC(uint64_t val); + void pcState(const TheISA::PCState &val) + { cpu->pcState(val, thread->threadId()); } - /** Reads this thread's next PC. */ - uint64_t readNextPC() - { return cpu->readNextPC(thread->readTid()); } + /** Needs to be implemented for future CheckerCPU support. + * See O3CPU for examples on how to integrate Checker. + */ + void pcStateNoRecord(const TheISA::PCState &val) + {} - /** Sets this thread's next PC. */ - void setNextPC(uint64_t val); + Addr instAddr() + { return cpu->instAddr(thread->threadId()); } - uint64_t readNextNPC() - { return cpu->readNextNPC(thread->readTid()); } + Addr nextInstAddr() + { return cpu->nextInstAddr(thread->threadId()); } - void setNextNPC(uint64_t val); + MicroPC microPC() + { return cpu->microPC(thread->threadId()); } /** Reads a miscellaneous register. */ MiscReg readMiscRegNoEffect(int misc_reg) - { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } + { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ MiscReg readMiscReg(int misc_reg) - { return cpu->readMiscReg(misc_reg, thread->readTid()); } + { return cpu->readMiscReg(misc_reg, thread->threadId()); } /** Sets a misc. register. */ void setMiscRegNoEffect(int misc_reg, const MiscReg &val); @@ -244,16 +265,22 @@ class InOrderThreadContext : public ThreadContext void setMiscReg(int misc_reg, const MiscReg &val); int flattenIntIndex(int reg) - { return cpu->isa[thread->readTid()].flattenIntIndex(reg); } + { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); } int flattenFloatIndex(int reg) - { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); } + { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); } - void activateContext(int delay) - { cpu->activateContext(thread->readTid(), delay); } + int flattenCCIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); } + + int flattenMiscIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); } + + void activateContext(Cycles delay) + { cpu->activateContext(thread->threadId(), delay); } void deallocateContext() - { cpu->deallocateContext(thread->readTid()); } + { cpu->deallocateContext(thread->threadId()); } /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. @@ -272,11 +299,9 @@ class InOrderThreadContext : public ThreadContext * misspeculating, this is set as false. */ bool misspeculating() { return false; } -#if !FULL_SYSTEM /** Executes a syscall in SE mode. */ void syscall(int64_t callnum) - { return cpu->syscall(callnum, thread->readTid()); } -#endif + { return cpu->syscall(callnum, thread->threadId()); } /** Reads the funcExeInst counter. */ Counter readFuncExeInst() { return thread->funcExeInst; } @@ -284,6 +309,18 @@ class InOrderThreadContext : public ThreadContext void changeRegFileContext(unsigned param, unsigned val) { panic("Not supported!"); } + + uint64_t readIntRegFlat(int idx); + void setIntRegFlat(int idx, uint64_t val); + + FloatReg readFloatRegFlat(int idx); + void setFloatRegFlat(int idx, FloatReg val); + + FloatRegBits readFloatRegBitsFlat(int idx); + void setFloatRegBitsFlat(int idx, FloatRegBits val); + + CCReg readCCRegFlat(int idx); + void setCCRegFlat(int idx, CCReg val); }; #endif