X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fozone%2Ffront_end_impl.hh;h=88413692761484b4dcf82403c931f4a75139530a;hb=69fc2af00600ced942d81dba082d9780e5325c9e;hp=6d02c58cb16bea4f83a04f00d81e25003dd75bdf;hpb=de90ae482507207566139c58911bc8e2894ad856;p=gem5.git

diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 6d02c58cb..884136927 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -28,12 +28,12 @@
  * Authors: Kevin Lim
  */
 
-#include "config/use_checker.hh"
-
 #include "sim/faults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
 #include "base/statistics.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/ozone/front_end.hh"
@@ -462,15 +462,10 @@ Fault
 FrontEnd<Impl>::fetchCacheLine()
 {
     // Read a cache line, based on the current PC.
-#if FULL_SYSTEM
-    // Flag to say whether or not address is physical addr.
-    unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
-#else
-    unsigned flags = 0;
-#endif // FULL_SYSTEM
     Fault fault = NoFault;
 
-    if (interruptPending && flags == 0) {
+    //AlphaDep
+    if (interruptPending && (PC & 0x3)) {
         return fault;
     }
 
@@ -481,11 +476,11 @@ FrontEnd<Impl>::fetchCacheLine()
 
     // Setup the memReq to do a read of the first isntruction's address.
     // Set the appropriate read size and flags as well.
-    memReq = new Request(0, fetch_PC, cacheBlkSize, flags,
-                         fetch_PC, cpu->readCpuId(), 0);
+    memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
+                         PC, cpu->thread->contextId());
 
     // Translate the instruction request.
-    fault = cpu->translateInstReq(memReq, thread);
+    fault = cpu->itb->translateAtomic(memReq, thread, false, true);
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.