X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fozone%2Ffront_end_impl.hh;h=88413692761484b4dcf82403c931f4a75139530a;hb=69fc2af00600ced942d81dba082d9780e5325c9e;hp=73ca6afbe4fe83ea03b897a4c7751470876dfee9;hpb=b5e68fb54677f601bb00c23af52db8fd6571301f;p=gem5.git

diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 73ca6afbe..884136927 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -28,12 +28,12 @@
  * Authors: Kevin Lim
  */
 
-#include "config/use_checker.hh"
-
 #include "sim/faults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
 #include "base/statistics.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/ozone/front_end.hh"
@@ -476,11 +476,11 @@ FrontEnd<Impl>::fetchCacheLine()
 
     // Setup the memReq to do a read of the first isntruction's address.
     // Set the appropriate read size and flags as well.
-    memReq = new Request(0, fetch_PC, cacheBlkSize, flags,
-                         fetch_PC, cpu->readCpuId(), 0);
+    memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
+                         PC, cpu->thread->contextId());
 
     // Translate the instruction request.
-    fault = cpu->translateInstReq(memReq, thread);
+    fault = cpu->itb->translateAtomic(memReq, thread, false, true);
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.