X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fsimple_thread.hh;h=189cbeec5ea3f5be18280b9672cb087fe18cdebd;hb=67fda02dda290d614de233846fee434b3713b1dc;hp=f2f79c070b3a424998b1aec26d1059c535bcdb27;hpb=91ca1b48e29dc8a5edcd57bf03ed9737b5de0661;p=gem5.git

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f2f79c070..189cbeec5 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -35,10 +35,10 @@
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/syscallreturn.hh"
+#include "arch/tlb.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
-#include "mem/physical.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/eventq.hh"
@@ -50,7 +50,6 @@ class BaseCPU;
 #if FULL_SYSTEM
 
 #include "sim/system.hh"
-#include "arch/tlb.hh"
 
 class FunctionProfile;
 class ProfileNode;
@@ -100,7 +99,7 @@ class SimpleThread : public ThreadState
     typedef ThreadContext::Status Status;
 
   protected:
-    RegFile regs;	// correct-path register context
+    RegFile regs;       // correct-path register context
 
   public:
     // pointer to CPU associated with this SimpleThread
@@ -110,10 +109,8 @@ class SimpleThread : public ThreadState
 
     System *system;
 
-#if FULL_SYSTEM
     TheISA::ITB *itb;
     TheISA::DTB *dtb;
-#endif
 
     // constructor: initialize SimpleThread from given process structure
 #if FULL_SYSTEM
@@ -121,7 +118,8 @@ class SimpleThread : public ThreadState
                  TheISA::ITB *_itb, TheISA::DTB *_dtb,
                  bool use_kernel_stats = true);
 #else
-    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
+    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
+                 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
 #endif
 
     SimpleThread();
@@ -150,10 +148,6 @@ class SimpleThread : public ThreadState
      */
     ThreadContext *getTC() { return tc; }
 
-#if FULL_SYSTEM
-    int getInstAsid() { return regs.instAsid(); }
-    int getDataAsid() { return regs.dataAsid(); }
-
     Fault translateInstReq(RequestPtr &req)
     {
         return itb->translate(req, tc);
@@ -169,27 +163,32 @@ class SimpleThread : public ThreadState
         return dtb->translate(req, tc, true);
     }
 
-    void dumpFuncProfile();
-
-    Fault hwrei();
-
-    bool simPalCheck(int palFunc);
-#else
-
-    Fault translateInstReq(RequestPtr &req)
+    void demapPage(Addr vaddr, uint64_t asn)
     {
-        return process->pTable->translate(req);
+        itb->demapPage(vaddr, asn);
+        dtb->demapPage(vaddr, asn);
     }
 
-    Fault translateDataReadReq(RequestPtr &req)
+    void demapInstPage(Addr vaddr, uint64_t asn)
     {
-        return process->pTable->translate(req);
+        itb->demapPage(vaddr, asn);
     }
 
-    Fault translateDataWriteReq(RequestPtr &req)
+    void demapDataPage(Addr vaddr, uint64_t asn)
     {
-        return process->pTable->translate(req);
+        dtb->demapPage(vaddr, asn);
     }
+
+#if FULL_SYSTEM
+    int getInstAsid() { return regs.instAsid(); }
+    int getDataAsid() { return regs.dataAsid(); }
+
+    void dumpFuncProfile();
+
+    Fault hwrei();
+
+    bool simPalCheck(int palFunc);
+
 #endif
 
     /*******************************************
@@ -200,21 +199,20 @@ class SimpleThread : public ThreadState
 
     int getThreadNum() { return tid; }
 
-#if FULL_SYSTEM
-    System *getSystemPtr() { return system; }
-
     TheISA::ITB *getITBPtr() { return itb; }
 
     TheISA::DTB *getDTBPtr() { return dtb; }
 
-    FunctionalPort *getPhysPort() { return physPort; }
+#if FULL_SYSTEM
+    System *getSystemPtr() { return system; }
 
-    /** Return a virtual port. If no thread context is specified then a static
-     * port is returned. Otherwise a port is created and returned. It must be
-     * deleted by deleteVirtPort(). */
-    VirtualPort *getVirtPort(ThreadContext *tc);
+    FunctionalPort *getPhysPort() { return physPort; }
 
-    void delVirtPort(VirtualPort *vp);
+    /** Return a virtual port. This port cannot be cached locally in an object.
+     * After a CPU switch it may point to the wrong memory object which could
+     * mean stale data.
+     */
+    VirtualPort *getVirtPort() { return virtPort; }
 #endif
 
     Status status() const { return _status; }
@@ -252,52 +250,62 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
+        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        return regs.readIntReg(flatIndex);
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
     {
-        return regs.readFloatReg(reg_idx, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatReg(flatIndex, width);
     }
 
     FloatReg readFloatReg(int reg_idx)
     {
-        return regs.readFloatReg(reg_idx);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatReg(flatIndex);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
     {
-        return regs.readFloatRegBits(reg_idx, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatRegBits(flatIndex, width);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
-        return regs.readFloatRegBits(reg_idx);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatRegBits(flatIndex);
     }
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
+        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        regs.setIntReg(flatIndex, val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
     {
-        regs.setFloatReg(reg_idx, val, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatReg(flatIndex, val, width);
     }
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        regs.setFloatReg(reg_idx, val);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatReg(flatIndex, val);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
     {
-        regs.setFloatRegBits(reg_idx, val, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatRegBits(flatIndex, val, width);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        regs.setFloatRegBits(reg_idx, val);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatRegBits(flatIndex, val);
     }
 
     uint64_t readPC()
@@ -350,24 +358,24 @@ class SimpleThread : public ThreadState
         regs.setNextNPC(val);
     }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
     {
-        return regs.readMiscReg(misc_reg);
+        return regs.readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
     {
-        return regs.readMiscRegWithEffect(misc_reg, tc);
+        return regs.readMiscReg(misc_reg, tc);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
-        return regs.setMiscReg(misc_reg, val);
+        return regs.setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, tc);
+        return regs.setMiscReg(misc_reg, val, tc);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
@@ -378,15 +386,17 @@ class SimpleThread : public ThreadState
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
+        assert(i < TheISA::NumArgumentRegs);
         return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg0 + i));
+                    TheISA::ArgumentReg[i]));
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, TheISA::IntReg val)
     {
+        assert(i < TheISA::NumArgumentRegs);
         regs.setIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg0 + i), val);
+                    TheISA::ArgumentReg[i]), val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)
@@ -399,12 +409,6 @@ class SimpleThread : public ThreadState
         process->syscall(callnum, tc);
     }
 #endif
-
-    void changeRegFileContext(TheISA::RegContextParam param,
-            TheISA::RegContextVal val)
-    {
-        regs.changeContext(param, val);
-    }
 };