X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fstatic_inst.hh;h=b2cd50851bf6256527052b920ec5127d466ef99e;hb=e656730f356edf86879abc522862c267c90ab3de;hp=4f3dd04fe8586eb3c10a8b3c23b4038f64ddfecf;hpb=2cfc24b8dc27acc0ef2ac421b79f839c0354fefd;p=gem5.git

diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 4f3dd04fe..b2cd50851 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -85,19 +85,14 @@ class InstRecord;
 class StaticInst : public RefCounted, public StaticInstFlags
 {
   public:
-    /// Binary extended machine instruction type.
-    typedef TheISA::ExtMachInst ExtMachInst;
-
-    enum {
-        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
-    };
+    using RegIdArrayPtr = RegId (StaticInst:: *)[];
 
   private:
-    /// See destRegIdx().
-    RegId _destRegIdx[MaxInstDestRegs];
     /// See srcRegIdx().
-    RegId _srcRegIdx[MaxInstSrcRegs];
+    RegIdArrayPtr _srcRegIdxPtr = nullptr;
+
+    /// See destRegIdx().
+    RegIdArrayPtr _destRegIdxPtr = nullptr;
 
   protected:
 
@@ -236,15 +231,23 @@ class StaticInst : public RefCounted, public StaticInstFlags
 
     /// Return logical index (architectural reg num) of i'th destination reg.
     /// Only the entries from 0 through numDestRegs()-1 are valid.
-    const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
+    const RegId &destRegIdx(int i) const { return (this->*_destRegIdxPtr)[i]; }
 
-    void setDestRegIdx(int i, const RegId &val) { _destRegIdx[i] = val; }
+    void
+    setDestRegIdx(int i, const RegId &val)
+    {
+        (this->*_destRegIdxPtr)[i] = val;
+    }
 
     /// Return logical index (architectural reg num) of i'th source reg.
     /// Only the entries from 0 through numSrcRegs()-1 are valid.
-    const RegId& srcRegIdx(int i)  const { return _srcRegIdx[i]; }
+    const RegId &srcRegIdx(int i) const { return (this->*_srcRegIdxPtr)[i]; }
 
-    void setSrcRegIdx(int i, const RegId &val) { _srcRegIdx[i] = val; }
+    void
+    setSrcRegIdx(int i, const RegId &val)
+    {
+        (this->*_srcRegIdxPtr)[i] = val;
+    }
 
     /// Pointer to a statically allocated "null" instruction object.
     static StaticInstPtr nullStaticInstPtr;
@@ -253,10 +256,25 @@ class StaticInst : public RefCounted, public StaticInstFlags
     static StaticInstPtr nopStaticInstPtr;
 
     /// The binary machine instruction.
-    const ExtMachInst machInst;
+    const TheISA::ExtMachInst machInst;
+
+    virtual uint64_t getEMI() const { return 0; }
 
   protected:
 
+    /**
+     * Set the pointers which point to the arrays of source and destination
+     * register indices. These will be defined in derived classes which know
+     * what size they need to be, and installed here so they can be accessed
+     * with the base class accessors.
+     */
+    void
+    setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
+    {
+        _srcRegIdxPtr = src;
+        _destRegIdxPtr = dest;
+    }
+
     /**
      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
      * methods.  Also useful to readily identify instructions from
@@ -282,11 +300,13 @@ class StaticInst : public RefCounted, public StaticInstFlags
     /// default, since the decoder generally only overrides
     /// the fields that are meaningful for the particular
     /// instruction.
-    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
-        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
-          _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
-          _numVecDestRegs(0), _numVecElemDestRegs(0), _numVecPredDestRegs(0),
-          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
+    StaticInst(const char *_mnemonic, TheISA::ExtMachInst _machInst,
+            OpClass __opClass)
+        : _opClass(__opClass),
+          _numSrcRegs(0), _numDestRegs(0), _numFPDestRegs(0),
+          _numIntDestRegs(0), _numCCDestRegs(0), _numVecDestRegs(0),
+          _numVecElemDestRegs(0), _numVecPredDestRegs(0), machInst(_machInst),
+          mnemonic(_mnemonic), cachedDisassembly(0)
     { }
 
   public: