X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fthread_context.hh;h=78ecdacf2d34ebffc888de44746911473211cd14;hb=9357e353fc976a409fb0cb3a875b402f452577f7;hp=e019e22bc33d516594f1d3c6367f23aab30d669a;hpb=44974a4462e019cfc5c65d20ad620faa9bc7f8cf;p=gem5.git

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index e019e22bc..78ecdacf2 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -31,17 +31,22 @@
 #ifndef __CPU_THREAD_CONTEXT_HH__
 #define __CPU_THREAD_CONTEXT_HH__
 
+#include "arch/registers.hh"
+#include "arch/types.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "mem/request.hh"
+#include "sim/byteswap.hh"
 #include "sim/faults.hh"
-#include "sim/host.hh"
 #include "sim/serialize.hh"
-#include "sim/byteswap.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
-class AlphaDTB;
-class AlphaITB;
+namespace TheISA
+{
+    class TLB;
+}
 class BaseCPU;
 class EndQuiesceEvent;
 class Event;
@@ -50,8 +55,10 @@ class FunctionalPort;
 class VirtualPort;
 class Process;
 class System;
-namespace Kernel {
-    class Statistics;
+namespace TheISA {
+    namespace Kernel {
+        class Statistics;
+    };
 };
 
 /**
@@ -73,22 +80,15 @@ namespace Kernel {
 class ThreadContext
 {
   protected:
-    typedef TheISA::RegFile RegFile;
     typedef TheISA::MachInst MachInst;
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
   public:
+
     enum Status
     {
-        /// Initialized but not running yet.  All CPUs start in
-        /// this state, but most transition to Active on cycle 1.
-        /// In MP or SMT systems, non-primary contexts will stay
-        /// in this state until a thread is assigned to them.
-        Unallocated,
-
         /// Running.  Instructions should be executed only when
         /// the context is in this state.
         Active,
@@ -107,24 +107,30 @@ class ThreadContext
 
     virtual BaseCPU *getCpuPtr() = 0;
 
-    virtual void setCpuId(int id) = 0;
+    virtual int cpuId() = 0;
 
-    virtual int readCpuId() = 0;
+    virtual int threadId() = 0;
 
-#if FULL_SYSTEM
-    virtual System *getSystemPtr() = 0;
+    virtual void setThreadId(int id) = 0;
 
-    virtual AlphaITB *getITBPtr() = 0;
+    virtual int contextId() = 0;
 
-    virtual AlphaDTB * getDTBPtr() = 0;
+    virtual void setContextId(int id) = 0;
 
-    virtual Kernel::Statistics *getKernelStats() = 0;
+    virtual TheISA::TLB *getITBPtr() = 0;
+
+    virtual TheISA::TLB *getDTBPtr() = 0;
+
+    virtual System *getSystemPtr() = 0;
+
+#if FULL_SYSTEM
+    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 
     virtual FunctionalPort *getPhysPort() = 0;
 
-    virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
+    virtual VirtualPort *getVirtPort() = 0;
 
-    virtual void delVirtPort(VirtualPort *vp) = 0;
+    virtual void connectMemPorts(ThreadContext *tc) = 0;
 #else
     virtual TranslatingPort *getMemPort() = 0;
 
@@ -140,13 +146,10 @@ class ThreadContext
     virtual void activate(int delay = 1) = 0;
 
     /// Set the status to Suspended.
-    virtual void suspend() = 0;
-
-    /// Set the status to Unallocated.
-    virtual void deallocate(int delay = 0) = 0;
+    virtual void suspend(int delay = 0) = 0;
 
     /// Set the status to Halted.
-    virtual void halt() = 0;
+    virtual void halt(int delay = 0) = 0;
 
 #if FULL_SYSTEM
     virtual void dumpFuncProfile() = 0;
@@ -171,8 +174,6 @@ class ThreadContext
     virtual void profileSample() = 0;
 #endif
 
-    virtual int getThreadNum() = 0;
-
     // Also somewhat obnoxious.  Really only used for the TLB fault.
     // However, may be quite useful in SPARC.
     virtual TheISA::MachInst getInst() = 0;
@@ -186,24 +187,16 @@ class ThreadContext
     //
     virtual uint64_t readIntReg(int reg_idx) = 0;
 
-    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
     virtual FloatReg readFloatReg(int reg_idx) = 0;
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 
     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
-
     virtual uint64_t readPC() = 0;
 
     virtual void setPC(uint64_t val) = 0;
@@ -216,13 +209,35 @@ class ThreadContext
 
     virtual void setNextNPC(uint64_t val) = 0;
 
+    virtual uint64_t readMicroPC() = 0;
+
+    virtual void setMicroPC(uint64_t val) = 0;
+
+    virtual uint64_t readNextMicroPC() = 0;
+
+    virtual void setNextMicroPC(uint64_t val) = 0;
+
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
-    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
+    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 
-    virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
+    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
-    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
+    virtual int flattenIntIndex(int reg) = 0;
+    virtual int flattenFloatIndex(int reg) = 0;
+
+    virtual uint64_t
+    readRegOtherThread(int misc_reg, ThreadID tid)
+    {
+        return 0;
+    }
+
+    virtual void
+    setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
+    {
+    }
 
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
@@ -230,32 +245,23 @@ class ThreadContext
 
     virtual void setStCondFailures(unsigned sc_failures) = 0;
 
-#if FULL_SYSTEM
-    virtual bool inPalMode() = 0;
-#endif
-
     // Only really makes sense for old CPU model.  Still could be useful though.
     virtual bool misspeculating() = 0;
 
 #if !FULL_SYSTEM
-    virtual IntReg getSyscallArg(int i) = 0;
-
-    // used to shift args for indirect syscall
-    virtual void setSyscallArg(int i, IntReg val) = 0;
-
-    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
-
     // Same with st cond failures.
     virtual Counter readFuncExeInst() = 0;
 
+    virtual void syscall(int64_t callnum) = 0;
+
     // This function exits the thread context in the CPU and returns
     // 1 if the CPU has no more active threads (meaning it's OK to exit);
     // Used in syscall-emulation mode when a  thread calls the exit syscall.
     virtual int exit() { return 1; };
 #endif
 
-    virtual void changeRegFileContext(RegFile::ContextParam param,
-            RegFile::ContextVal val) = 0;
+    /** function to compare two thread contexts (for debugging) */
+    static void compare(ThreadContext *one, ThreadContext *two);
 };
 
 /**
@@ -282,24 +288,31 @@ class ProxyThreadContext : public ThreadContext
 
     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 
-    void setCpuId(int id) { actualTC->setCpuId(id); }
+    int cpuId() { return actualTC->cpuId(); }
 
-    int readCpuId() { return actualTC->readCpuId(); }
+    int threadId() { return actualTC->threadId(); }
 
-#if FULL_SYSTEM
-    System *getSystemPtr() { return actualTC->getSystemPtr(); }
+    void setThreadId(int id) { return actualTC->setThreadId(id); }
+
+    int contextId() { return actualTC->contextId(); }
 
-    AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
+    void setContextId(int id) { actualTC->setContextId(id); }
 
-    AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+
+    System *getSystemPtr() { return actualTC->getSystemPtr(); }
+
+#if FULL_SYSTEM
+    TheISA::Kernel::Statistics *getKernelStats()
+    { return actualTC->getKernelStats(); }
 
     FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 
-    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
+    VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
 
-    void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
+    void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 #else
     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 
@@ -315,13 +328,10 @@ class ProxyThreadContext : public ThreadContext
     void activate(int delay = 1) { actualTC->activate(delay); }
 
     /// Set the status to Suspended.
-    void suspend() { actualTC->suspend(); }
-
-    /// Set the status to Unallocated.
-    void deallocate(int delay = 0) { actualTC->deallocate(); }
+    void suspend(int delay = 0) { actualTC->suspend(); }
 
     /// Set the status to Halted.
-    void halt() { actualTC->halt(); }
+    void halt(int delay = 0) { actualTC->halt(); }
 
 #if FULL_SYSTEM
     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
@@ -345,9 +355,6 @@ class ProxyThreadContext : public ThreadContext
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
 #endif
-
-    int getThreadNum() { return actualTC->getThreadNum(); }
-
     // @todo: Do I need this?
     MachInst getInst() { return actualTC->getInst(); }
 
@@ -362,30 +369,18 @@ class ProxyThreadContext : public ThreadContext
     uint64_t readIntReg(int reg_idx)
     { return actualTC->readIntReg(reg_idx); }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualTC->readFloatReg(reg_idx, width); }
-
     FloatReg readFloatReg(int reg_idx)
     { return actualTC->readFloatReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualTC->readFloatRegBits(reg_idx, width); }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
     void setIntReg(int reg_idx, uint64_t val)
     { actualTC->setIntReg(reg_idx, val); }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    { actualTC->setFloatReg(reg_idx, val, width); }
-
     void setFloatReg(int reg_idx, FloatReg val)
     { actualTC->setFloatReg(reg_idx, val); }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    { actualTC->setFloatRegBits(reg_idx, val, width); }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     { actualTC->setFloatRegBits(reg_idx, val); }
 
@@ -401,48 +396,47 @@ class ProxyThreadContext : public ThreadContext
 
     void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 
+    uint64_t readMicroPC() { return actualTC->readMicroPC(); }
+
+    void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
+
+    uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
+
+    void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
+
+    MiscReg readMiscRegNoEffect(int misc_reg)
+    { return actualTC->readMiscRegNoEffect(misc_reg); }
+
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    { return actualTC->setMiscRegWithEffect(misc_reg, val); }
+    int flattenIntIndex(int reg)
+    { return actualTC->flattenIntIndex(reg); }
+
+    int flattenFloatIndex(int reg)
+    { return actualTC->flattenFloatIndex(reg); }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
 
     void setStCondFailures(unsigned sc_failures)
     { actualTC->setStCondFailures(sc_failures); }
-#if FULL_SYSTEM
-    bool inPalMode() { return actualTC->inPalMode(); }
-#endif
 
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }
 
 #if !FULL_SYSTEM
-    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
-
-    // used to shift args for indirect syscall
-    void setSyscallArg(int i, IntReg val)
-    { actualTC->setSyscallArg(i, val); }
-
-    void setSyscallReturn(SyscallReturn return_value)
-    { actualTC->setSyscallReturn(return_value); }
+    void syscall(int64_t callnum)
+    { actualTC->syscall(callnum); }
 
     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 #endif
-
-    void changeRegFileContext(RegFile::ContextParam param,
-            RegFile::ContextVal val)
-    {
-        actualTC->changeRegFileContext(param, val);
-    }
 };
 
 #endif