X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fthread_context.hh;h=7c3f11c12972afecc0cb71cd91992efccba1a986;hb=cf4a00ca410226d3fd1b4db816938b7ddf78a333;hp=70d70514419b29ac9e63f00f75235c853fcf17b9;hpb=b973fae85d47a8184204d5d38b32ad3d427ce41c;p=gem5.git diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 70d705144..7c3f11c12 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -31,17 +31,23 @@ #ifndef __CPU_THREAD_CONTEXT_HH__ #define __CPU_THREAD_CONTEXT_HH__ +#include "arch/regfile.hh" +#include "arch/types.hh" #include "config/full_system.hh" #include "mem/request.hh" #include "sim/faults.hh" #include "sim/host.hh" #include "sim/serialize.hh" +#include "sim/syscallreturn.hh" #include "sim/byteswap.hh" // @todo: Figure out a more architecture independent way to obtain the ITB and // DTB pointers. -class AlphaDTB; -class AlphaITB; +namespace TheISA +{ + class DTB; + class ITB; +} class BaseCPU; class EndQuiesceEvent; class Event; @@ -50,8 +56,10 @@ class FunctionalPort; class VirtualPort; class Process; class System; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; /** @@ -107,24 +115,30 @@ class ThreadContext virtual BaseCPU *getCpuPtr() = 0; - virtual void setCpuId(int id) = 0; + virtual int cpuId() = 0; - virtual int readCpuId() = 0; + virtual int threadId() = 0; -#if FULL_SYSTEM - virtual System *getSystemPtr() = 0; + virtual void setThreadId(int id) = 0; + + virtual int contextId() = 0; - virtual AlphaITB *getITBPtr() = 0; + virtual void setContextId(int id) = 0; - virtual AlphaDTB * getDTBPtr() = 0; + virtual TheISA::ITB *getITBPtr() = 0; - virtual Kernel::Statistics *getKernelStats() = 0; + virtual TheISA::DTB *getDTBPtr() = 0; + + virtual System *getSystemPtr() = 0; + +#if FULL_SYSTEM + virtual TheISA::Kernel::Statistics *getKernelStats() = 0; virtual FunctionalPort *getPhysPort() = 0; - virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; + virtual VirtualPort *getVirtPort() = 0; - virtual void delVirtPort(VirtualPort *vp) = 0; + virtual void connectMemPorts(ThreadContext *tc) = 0; #else virtual TranslatingPort *getMemPort() = 0; @@ -140,13 +154,13 @@ class ThreadContext virtual void activate(int delay = 1) = 0; /// Set the status to Suspended. - virtual void suspend() = 0; + virtual void suspend(int delay = 0) = 0; /// Set the status to Unallocated. - virtual void deallocate() = 0; + virtual void deallocate(int delay = 0) = 0; /// Set the status to Halted. - virtual void halt() = 0; + virtual void halt(int delay = 0) = 0; #if FULL_SYSTEM virtual void dumpFuncProfile() = 0; @@ -171,8 +185,6 @@ class ThreadContext virtual void profileSample() = 0; #endif - virtual int getThreadNum() = 0; - // Also somewhat obnoxious. Really only used for the TLB fault. // However, may be quite useful in SPARC. virtual TheISA::MachInst getInst() = 0; @@ -216,13 +228,25 @@ class ThreadContext virtual void setNextNPC(uint64_t val) = 0; + virtual uint64_t readMicroPC() = 0; + + virtual void setMicroPC(uint64_t val) = 0; + + virtual uint64_t readNextMicroPC() = 0; + + virtual void setNextMicroPC(uint64_t val) = 0; + + virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; + virtual MiscReg readMiscReg(int misc_reg) = 0; - virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; + virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; - virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; - virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; + virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } + + virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. @@ -230,10 +254,6 @@ class ThreadContext virtual void setStCondFailures(unsigned sc_failures) = 0; -#if FULL_SYSTEM - virtual bool inPalMode() = 0; -#endif - // Only really makes sense for old CPU model. Still could be useful though. virtual bool misspeculating() = 0; @@ -248,14 +268,16 @@ class ThreadContext // Same with st cond failures. virtual Counter readFuncExeInst() = 0; + virtual void syscall(int64_t callnum) = 0; + // This function exits the thread context in the CPU and returns // 1 if the CPU has no more active threads (meaning it's OK to exit); // Used in syscall-emulation mode when a thread calls the exit syscall. virtual int exit() { return 1; }; #endif - virtual void changeRegFileContext(RegFile::ContextParam param, - RegFile::ContextVal val) = 0; + /** function to compare two thread contexts (for debugging) */ + static void compare(ThreadContext *one, ThreadContext *two); }; /** @@ -282,24 +304,31 @@ class ProxyThreadContext : public ThreadContext BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } - void setCpuId(int id) { actualTC->setCpuId(id); } + int cpuId() { return actualTC->cpuId(); } - int readCpuId() { return actualTC->readCpuId(); } + int threadId() { return actualTC->threadId(); } -#if FULL_SYSTEM - System *getSystemPtr() { return actualTC->getSystemPtr(); } + void setThreadId(int id) { return actualTC->setThreadId(id); } + + int contextId() { return actualTC->contextId(); } + + void setContextId(int id) { actualTC->setContextId(id); } + + TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } - AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } + TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } - AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } + System *getSystemPtr() { return actualTC->getSystemPtr(); } - Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } +#if FULL_SYSTEM + TheISA::Kernel::Statistics *getKernelStats() + { return actualTC->getKernelStats(); } FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } - VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } + VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } - void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } + void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } #else TranslatingPort *getMemPort() { return actualTC->getMemPort(); } @@ -315,13 +344,13 @@ class ProxyThreadContext : public ThreadContext void activate(int delay = 1) { actualTC->activate(delay); } /// Set the status to Suspended. - void suspend() { actualTC->suspend(); } + void suspend(int delay = 0) { actualTC->suspend(); } /// Set the status to Unallocated. - void deallocate() { actualTC->deallocate(); } + void deallocate(int delay = 0) { actualTC->deallocate(); } /// Set the status to Halted. - void halt() { actualTC->halt(); } + void halt(int delay = 0) { actualTC->halt(); } #if FULL_SYSTEM void dumpFuncProfile() { actualTC->dumpFuncProfile(); } @@ -345,9 +374,6 @@ class ProxyThreadContext : public ThreadContext void profileClear() { return actualTC->profileClear(); } void profileSample() { return actualTC->profileSample(); } #endif - - int getThreadNum() { return actualTC->getThreadNum(); } - // @todo: Do I need this? MachInst getInst() { return actualTC->getInst(); } @@ -401,26 +427,31 @@ class ProxyThreadContext : public ThreadContext void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } + uint64_t readMicroPC() { return actualTC->readMicroPC(); } + + void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } + + uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } + + void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } + + MiscReg readMiscRegNoEffect(int misc_reg) + { return actualTC->readMiscRegNoEffect(misc_reg); } + MiscReg readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return actualTC->readMiscRegWithEffect(misc_reg, fault); } + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + { return actualTC->setMiscRegNoEffect(misc_reg, val); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { return actualTC->setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) - { return actualTC->setMiscRegWithEffect(misc_reg, val); } - unsigned readStCondFailures() { return actualTC->readStCondFailures(); } void setStCondFailures(unsigned sc_failures) { actualTC->setStCondFailures(sc_failures); } -#if FULL_SYSTEM - bool inPalMode() { return actualTC->inPalMode(); } -#endif // @todo: Fix this! bool misspeculating() { return actualTC->misspeculating(); } @@ -435,14 +466,11 @@ class ProxyThreadContext : public ThreadContext void setSyscallReturn(SyscallReturn return_value) { actualTC->setSyscallReturn(return_value); } + void syscall(int64_t callnum) + { actualTC->syscall(callnum); } + Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } #endif - - void changeRegFileContext(RegFile::ContextParam param, - RegFile::ContextVal val) - { - actualTC->changeRegFileContext(param, val); - } }; #endif