X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fcpu%2Fthread_context.hh;h=dbe3c0ce83e2bb3f9449b257d789e79f5bf0179c;hb=10f1f8c6a49fa96ffb420eaa8cdd3641128ec9ec;hp=16e491fd392058f3e72269daa151d1f6c3d601cb;hpb=1352e55ceb2d78a9a36451636b672cd6daf8550e;p=gem5.git

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 16e491fd3..dbe3c0ce8 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011-2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -31,36 +43,35 @@
 #ifndef __CPU_THREAD_CONTEXT_HH__
 #define __CPU_THREAD_CONTEXT_HH__
 
-#include "arch/regfile.hh"
+#include <iostream>
+#include <string>
+
+#include "arch/registers.hh"
 #include "arch/types.hh"
-#include "config/full_system.hh"
-#include "mem/request.hh"
-#include "sim/faults.hh"
-#include "sim/host.hh"
-#include "sim/serialize.hh"
-#include "sim/syscallreturn.hh"
-#include "sim/byteswap.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
 namespace TheISA
 {
-    class DTB;
-    class ITB;
+    class Decoder;
+    class TLB;
 }
 class BaseCPU;
+class CheckerCPU;
+class Checkpoint;
 class EndQuiesceEvent;
-class Event;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
+class SETranslatingPortProxy;
+class FSTranslatingPortProxy;
+class PortProxy;
 class Process;
 class System;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * ThreadContext is the external interface to all thread state for
@@ -81,22 +92,15 @@ namespace TheISA {
 class ThreadContext
 {
   protected:
-    typedef TheISA::RegFile RegFile;
     typedef TheISA::MachInst MachInst;
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
   public:
+
     enum Status
     {
-        /// Initialized but not running yet.  All CPUs start in
-        /// this state, but most transition to Active on cycle 1.
-        /// In MP or SMT systems, non-primary contexts will stay
-        /// in this state until a thread is assigned to them.
-        Unallocated,
-
         /// Running.  Instructions should be executed only when
         /// the context is in this state.
         Active,
@@ -115,31 +119,43 @@ class ThreadContext
 
     virtual BaseCPU *getCpuPtr() = 0;
 
-    virtual void setCpuId(int id) = 0;
+    virtual int cpuId() = 0;
 
-    virtual int readCpuId() = 0;
+    virtual int threadId() = 0;
 
-#if FULL_SYSTEM
-    virtual System *getSystemPtr() = 0;
+    virtual void setThreadId(int id) = 0;
+
+    virtual int contextId() = 0;
 
-    virtual TheISA::ITB *getITBPtr() = 0;
+    virtual void setContextId(int id) = 0;
 
-    virtual TheISA::DTB *getDTBPtr() = 0;
+    virtual TheISA::TLB *getITBPtr() = 0;
+
+    virtual TheISA::TLB *getDTBPtr() = 0;
+
+    virtual CheckerCPU *getCheckerCpuPtr() = 0;
+
+    virtual TheISA::Decoder *getDecoderPtr() = 0;
+
+    virtual System *getSystemPtr() = 0;
 
     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 
-    virtual FunctionalPort *getPhysPort() = 0;
+    virtual PortProxy &getPhysProxy() = 0;
 
-    virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
+    virtual FSTranslatingPortProxy &getVirtProxy() = 0;
 
-    virtual void delVirtPort(VirtualPort *vp) = 0;
+    /**
+     * Initialise the physical and virtual port proxies and tie them to
+     * the data port of the CPU.
+     *
+     * tc ThreadContext for the virtual-to-physical translation
+     */
+    virtual void initMemProxies(ThreadContext *tc) = 0;
 
-    virtual void connectMemPorts() = 0;
-#else
-    virtual TranslatingPort *getMemPort() = 0;
+    virtual SETranslatingPortProxy &getMemProxy() = 0;
 
     virtual Process *getProcessPtr() = 0;
-#endif
 
     virtual Status status() const = 0;
 
@@ -147,29 +163,20 @@ class ThreadContext
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    virtual void activate(int delay = 1) = 0;
+    virtual void activate(Cycles delay = Cycles(1)) = 0;
 
     /// Set the status to Suspended.
-    virtual void suspend() = 0;
-
-    /// Set the status to Unallocated.
-    virtual void deallocate(int delay = 0) = 0;
+    virtual void suspend(Cycles delay = Cycles(0)) = 0;
 
     /// Set the status to Halted.
-    virtual void halt() = 0;
+    virtual void halt(Cycles delay = Cycles(0)) = 0;
 
-#if FULL_SYSTEM
     virtual void dumpFuncProfile() = 0;
-#endif
 
     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 
     virtual void regStats(const std::string &name) = 0;
 
-    virtual void serialize(std::ostream &os) = 0;
-    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
-
-#if FULL_SYSTEM
     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 
     // Not necessarily the best location for these...
@@ -179,13 +186,6 @@ class ThreadContext
 
     virtual void profileClear() = 0;
     virtual void profileSample() = 0;
-#endif
-
-    virtual int getThreadNum() = 0;
-
-    // Also somewhat obnoxious.  Really only used for the TLB fault.
-    // However, may be quite useful in SPARC.
-    virtual TheISA::MachInst getInst() = 0;
 
     virtual void copyArchRegs(ThreadContext *tc) = 0;
 
@@ -196,43 +196,49 @@ class ThreadContext
     //
     virtual uint64_t readIntReg(int reg_idx) = 0;
 
-    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
     virtual FloatReg readFloatReg(int reg_idx) = 0;
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 
     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
+    virtual TheISA::PCState pcState() = 0;
 
-    virtual uint64_t readPC() = 0;
+    virtual void pcState(const TheISA::PCState &val) = 0;
 
-    virtual void setPC(uint64_t val) = 0;
+    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
 
-    virtual uint64_t readNextPC() = 0;
+    virtual Addr instAddr() = 0;
 
-    virtual void setNextPC(uint64_t val) = 0;
+    virtual Addr nextInstAddr() = 0;
 
-    virtual uint64_t readNextNPC() = 0;
+    virtual MicroPC microPC() = 0;
 
-    virtual void setNextNPC(uint64_t val) = 0;
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
 
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
-    virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
+    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
-    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
+    virtual int flattenIntIndex(int reg) = 0;
+    virtual int flattenFloatIndex(int reg) = 0;
+
+    virtual uint64_t
+    readRegOtherThread(int misc_reg, ThreadID tid)
+    {
+        return 0;
+    }
+
+    virtual void
+    setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
+    {
+    }
 
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
@@ -243,25 +249,42 @@ class ThreadContext
     // Only really makes sense for old CPU model.  Still could be useful though.
     virtual bool misspeculating() = 0;
 
-#if !FULL_SYSTEM
-    virtual IntReg getSyscallArg(int i) = 0;
-
-    // used to shift args for indirect syscall
-    virtual void setSyscallArg(int i, IntReg val) = 0;
-
-    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
-
     // Same with st cond failures.
     virtual Counter readFuncExeInst() = 0;
 
+    virtual void syscall(int64_t callnum) = 0;
+
     // This function exits the thread context in the CPU and returns
     // 1 if the CPU has no more active threads (meaning it's OK to exit);
     // Used in syscall-emulation mode when a  thread calls the exit syscall.
     virtual int exit() { return 1; };
-#endif
 
-    virtual void changeRegFileContext(TheISA::RegContextParam param,
-            TheISA::RegContextVal val) = 0;
+    /** function to compare two thread contexts (for debugging) */
+    static void compare(ThreadContext *one, ThreadContext *two);
+
+    /** @{ */
+    /**
+     * Flat register interfaces
+     *
+     * Some architectures have different registers visible in
+     * different modes. Such architectures "flatten" a register (see
+     * flattenIntIndex() and flattenFloatIndex()) to map it into the
+     * gem5 register file. This interface provides a flat interface to
+     * the underlying register file, which allows for example
+     * serialization code to access all registers.
+     */
+
+    virtual uint64_t readIntRegFlat(int idx) = 0;
+    virtual void setIntRegFlat(int idx, uint64_t val) = 0;
+
+    virtual FloatReg readFloatRegFlat(int idx) = 0;
+    virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
+
+    virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
+    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
+
+    /** @} */
+
 };
 
 /**
@@ -288,32 +311,38 @@ class ProxyThreadContext : public ThreadContext
 
     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 
-    void setCpuId(int id) { actualTC->setCpuId(id); }
+    int cpuId() { return actualTC->cpuId(); }
 
-    int readCpuId() { return actualTC->readCpuId(); }
+    int threadId() { return actualTC->threadId(); }
 
-#if FULL_SYSTEM
-    System *getSystemPtr() { return actualTC->getSystemPtr(); }
+    void setThreadId(int id) { return actualTC->setThreadId(id); }
+
+    int contextId() { return actualTC->contextId(); }
+
+    void setContextId(int id) { actualTC->setContextId(id); }
+
+    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
+
+    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+    CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
 
-    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+
+    System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
 
-    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
 
-    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
+    FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
 
-    void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
+    void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
 
-    void connectMemPorts() { actualTC->connectMemPorts(); }
-#else
-    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
 
     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-#endif
 
     Status status() const { return actualTC->status(); }
 
@@ -321,31 +350,22 @@ class ProxyThreadContext : public ThreadContext
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    void activate(int delay = 1) { actualTC->activate(delay); }
+    void activate(Cycles delay = Cycles(1))
+    { actualTC->activate(delay); }
 
     /// Set the status to Suspended.
-    void suspend() { actualTC->suspend(); }
-
-    /// Set the status to Unallocated.
-    void deallocate(int delay = 0) { actualTC->deallocate(); }
+    void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
 
     /// Set the status to Halted.
-    void halt() { actualTC->halt(); }
+    void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
 
-#if FULL_SYSTEM
     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
 
     void takeOverFrom(ThreadContext *oldContext)
     { actualTC->takeOverFrom(oldContext); }
 
     void regStats(const std::string &name) { actualTC->regStats(name); }
 
-    void serialize(std::ostream &os) { actualTC->serialize(os); }
-    void unserialize(Checkpoint *cp, const std::string &section)
-    { actualTC->unserialize(cp, section); }
-
-#if FULL_SYSTEM
     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 
     Tick readLastActivate() { return actualTC->readLastActivate(); }
@@ -353,12 +373,6 @@ class ProxyThreadContext : public ThreadContext
 
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
-#endif
-
-    int getThreadNum() { return actualTC->getThreadNum(); }
-
-    // @todo: Do I need this?
-    MachInst getInst() { return actualTC->getInst(); }
 
     // @todo: Do I need this?
     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
@@ -371,56 +385,53 @@ class ProxyThreadContext : public ThreadContext
     uint64_t readIntReg(int reg_idx)
     { return actualTC->readIntReg(reg_idx); }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualTC->readFloatReg(reg_idx, width); }
-
     FloatReg readFloatReg(int reg_idx)
     { return actualTC->readFloatReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualTC->readFloatRegBits(reg_idx, width); }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
     void setIntReg(int reg_idx, uint64_t val)
     { actualTC->setIntReg(reg_idx, val); }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    { actualTC->setFloatReg(reg_idx, val, width); }
-
     void setFloatReg(int reg_idx, FloatReg val)
     { actualTC->setFloatReg(reg_idx, val); }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    { actualTC->setFloatRegBits(reg_idx, val, width); }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     { actualTC->setFloatRegBits(reg_idx, val); }
 
-    uint64_t readPC() { return actualTC->readPC(); }
+    TheISA::PCState pcState() { return actualTC->pcState(); }
+
+    void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 
-    void setPC(uint64_t val) { actualTC->setPC(val); }
+    void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
 
-    uint64_t readNextPC() { return actualTC->readNextPC(); }
+    Addr instAddr() { return actualTC->instAddr(); }
+    Addr nextInstAddr() { return actualTC->nextInstAddr(); }
+    MicroPC microPC() { return actualTC->microPC(); }
 
-    void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
+    bool readPredicate() { return actualTC->readPredicate(); }
 
-    uint64_t readNextNPC() { return actualTC->readNextNPC(); }
+    void setPredicate(bool val)
+    { actualTC->setPredicate(val); }
 
-    void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
+    MiscReg readMiscRegNoEffect(int misc_reg)
+    { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
-    { return actualTC->readMiscRegWithEffect(misc_reg); }
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 
     void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    { return actualTC->setMiscRegWithEffect(misc_reg, val); }
+    int flattenIntIndex(int reg)
+    { return actualTC->flattenIntIndex(reg); }
+
+    int flattenFloatIndex(int reg)
+    { return actualTC->flattenFloatIndex(reg); }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
@@ -431,24 +442,56 @@ class ProxyThreadContext : public ThreadContext
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }
 
-#if !FULL_SYSTEM
-    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
+    void syscall(int64_t callnum)
+    { actualTC->syscall(callnum); }
 
-    // used to shift args for indirect syscall
-    void setSyscallArg(int i, IntReg val)
-    { actualTC->setSyscallArg(i, val); }
+    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 
-    void setSyscallReturn(SyscallReturn return_value)
-    { actualTC->setSyscallReturn(return_value); }
+    uint64_t readIntRegFlat(int idx)
+    { return actualTC->readIntRegFlat(idx); }
 
-    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
+    void setIntRegFlat(int idx, uint64_t val)
+    { actualTC->setIntRegFlat(idx, val); }
 
-    void changeRegFileContext(TheISA::RegContextParam param,
-            TheISA::RegContextVal val)
-    {
-        actualTC->changeRegFileContext(param, val);
-    }
+    FloatReg readFloatRegFlat(int idx)
+    { return actualTC->readFloatRegFlat(idx); }
+
+    void setFloatRegFlat(int idx, FloatReg val)
+    { actualTC->setFloatRegFlat(idx, val); }
+
+    FloatRegBits readFloatRegBitsFlat(int idx)
+    { return actualTC->readFloatRegBitsFlat(idx); }
+
+    void setFloatRegBitsFlat(int idx, FloatRegBits val)
+    { actualTC->setFloatRegBitsFlat(idx, val); }
 };
 
+/** @{ */
+/**
+ * Thread context serialization helpers
+ *
+ * These helper functions provide a way to the data in a
+ * ThreadContext. They are provided as separate helper function since
+ * implementing them as members of the ThreadContext interface would
+ * be confusing when the ThreadContext is exported via a proxy.
+ */
+
+void serialize(ThreadContext &tc, std::ostream &os);
+void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section);
+
+/** @} */
+
+
+/**
+ * Copy state between thread contexts in preparation for CPU handover.
+ *
+ * @note This method modifies the old thread contexts as well as the
+ * new thread context. The old thread context will have its quiesce
+ * event descheduled if it is scheduled and its status set to halted.
+ *
+ * @param new_tc Destination ThreadContext.
+ * @param old_tc Source ThreadContext.
+ */
+void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
+
 #endif