X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2FEthernet.py;h=5821a3e96febb32c4b8060e39db512780a9cf479;hb=27e8f3c98a4b1c56e16ce5f80c7ad992083ccef9;hp=bef9a0a2012102fc3fb325f72774987d0f179c8a;hpb=773cb77656174b221c1e51b92a8af7d8e268b733;p=gem5.git

diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index bef9a0a20..5821a3e96 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Pci import PciDevice, PciConfigData
+from Pci import PciDevice
 
 class EtherObject(SimObject):
     type = 'EtherObject'
@@ -79,8 +79,6 @@ class IGbE(EtherDevice):
     tx_desc_cache_size = Param.Int(64,
         "Number of enteries in the rx descriptor cache")
     clock = Param.Clock('500MHz', "Clock speed of the device")
-
-class IGbEPciData(PciConfigData):
     VendorID = 0x8086
     DeviceID = 0x1075
     SubsystemID = 0x1008
@@ -100,6 +98,13 @@ class IGbEPciData(PciConfigData):
     InterruptLine = 0x1e
     InterruptPin = 0x01
     BAR0Size = '128kB'
+    wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
+    fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
+    fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
+    wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
+    tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
+    rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
+
 
 class EtherDevBase(EtherDevice):
     type = 'EtherDevBase'
@@ -125,7 +130,13 @@ class EtherDevBase(EtherDevice):
     tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
     rss = Param.Bool(False, "Receive Side Scaling")
 
-class NSGigEPciData(PciConfigData):
+class NSGigE(EtherDevBase):
+    type = 'NSGigE'
+
+    dma_data_free = Param.Bool(False, "DMA of Data is free")
+    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+
     VendorID = 0x100B
     DeviceID = 0x0022
     Status = 0x0290
@@ -145,17 +156,27 @@ class NSGigEPciData(PciConfigData):
     BAR0Size = '256B'
     BAR1Size = '4kB'
 
-class NSGigE(EtherDevBase):
-    type = 'NSGigE'
 
-    dma_data_free = Param.Bool(False, "DMA of Data is free")
-    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
-    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 
-    configdata = NSGigEPciData()
+class Sinic(EtherDevBase):
+    type = 'Sinic'
+    cxx_class = 'Sinic::Device'
 
+    rx_max_copy = Param.MemorySize('1514B', "rx max copy")
+    tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+    rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
+    rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
+    rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
+    tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
+    tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
+    virtual_count = Param.UInt32(1, "Virtualized SINIC")
+    zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
+    zero_copy_threshold = Param.UInt32(256,
+        "Only zero copy above this threshold")
+    zero_copy = Param.Bool(False, "Zero copy receive")
+    delay_copy = Param.Bool(False, "Delayed copy transmit")
+    virtual_addr = Param.Bool(False, "Virtual addressing")
 
-class SinicPciData(PciConfigData):
     VendorID = 0x1291
     DeviceID = 0x1293
     Status = 0x0290
@@ -174,22 +195,4 @@ class SinicPciData(PciConfigData):
     InterruptPin = 0x01
     BAR0Size = '64kB'
 
-class Sinic(EtherDevBase):
-    type = 'Sinic'
-    cxx_namespace = 'Sinic'
-    cxx_class = 'Device'
-
-    rx_max_copy = Param.MemorySize('1514B', "rx max copy")
-    tx_max_copy = Param.MemorySize('16kB', "tx max copy")
-    rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
-    rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
-    rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
-    tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
-    tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
-    virtual_count = Param.UInt32(1, "Virtualized SINIC")
-    zero_copy = Param.Bool(False, "Zero copy receive")
-    delay_copy = Param.Bool(False, "Delayed copy transmit")
-    virtual_addr = Param.Bool(False, "Virtual addressing")
-
-    configdata = SinicPciData()