X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2Falpha%2Ftsunami_cchip.cc;h=fd76fd93e8b8f8236632b27764e38a0852ad155d;hb=d9f39c8ce75aac84c88b32392c2967344362906b;hp=a7175d90c9cdaa553c6fab6c5056d02be8950ad6;hpb=855b3216f21453807c1b6fedab0e49aa36128a80;p=gem5.git

diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index a7175d90c..fd76fd93e 100644
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -39,6 +39,7 @@
 
 #include "arch/alpha/ev5.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
 #include "cpu/thread_context.hh"
 #include "dev/alpha/tsunami.hh"
@@ -47,14 +48,14 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/TsunamiCChip.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiCChip::TsunamiCChip(Params *p)
+TsunamiCChip::TsunamiCChip(const Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami)
 {
     pioSize = 0x10000000;
@@ -109,8 +110,14 @@ TsunamiCChip::read(PacketPtr pkt)
                   panic("TSDEV_CC_MTR not implemeted\n");
                    break;
               case TSDEV_CC_MISC:
-                  pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
-                                     (pkt->req->getCpuNum() & 0x3));
+                  pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
+                                     (pkt->req->contextId() & 0x3));
+                  // currently, FS cannot handle MT so contextId and
+                  // cpuId are effectively the same, don't know if it will
+                  // matter if FS becomes MT enabled.  I suspect no because
+                  // we are currently able to boot up to 64 procs anyway
+                  // which would render the CPUID of this register useless
+                  // anyway
                   break;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
@@ -452,7 +459,7 @@ TsunamiCChip::postRTC()
        if (!(cpumask & itint)) {
            itint |= cpumask;
            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
-           DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
+           DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
        }
     }
 
@@ -521,36 +528,8 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(drir);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-CREATE_SIM_OBJECT(TsunamiCChip)
+TsunamiCChip *
+TsunamiCChipParams::create()
 {
-    TsunamiCChip::Params *p = new TsunamiCChip::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->tsunami = tsunami;
-    return new TsunamiCChip(p);
+    return new TsunamiCChip(this);
 }
-
-REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)