X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2Fi8254xGBe.cc;h=0fbda1897a67a37699202450f273bbbf48e66775;hb=27e8f3c98a4b1c56e16ce5f80c7ad992083ccef9;hp=3b197043226ab2a1b06d04f2ccbe362763b02b48;hpb=1099a9838abcb158b47714c800a9666eb82c97ea;p=gem5.git

diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 3b1970432..0fbda1897 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -57,10 +57,15 @@ using namespace Net;
 IGbE::IGbE(const Params *p)
     : EtherDevice(p), etherInt(NULL),  drainEvent(NULL), useFlowControl(p->use_flow_control),
       rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
-      txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
+      txTick(false), txFifoTick(false), rxDmaPacket(false), 
+      fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), 
+      fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), 
+      rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),  
+      rdtrEvent(this), radvEvent(this),
       tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
       rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
-      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
+      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
+      clock(p->clock), lastInterrupt(0)
 {
     etherInt = new IGbEInt(name() + ".int", this);
 
@@ -580,17 +585,23 @@ IGbE::postInterrupt(IntTypes t, bool now)
         return;
 
     regs.icr = regs.icr() | t;
-    if (regs.itr.interval() == 0 || now) {
+
+    Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
+    DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
+            curTick, regs.itr.interval(), itr_interval);
+
+    if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <= curTick) {
         if (interEvent.scheduled()) {
-            interEvent.deschedule();
+            deschedule(interEvent);
         }
-        postedInterrupts++;
         cpuPostInt();
     } else {
-       DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
-                Clock::Int::ns * 256 * regs.itr.interval());
+       Tick int_time = lastInterrupt + itr_interval;
+       assert(int_time > 0);
+       DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
+                int_time);
        if (!interEvent.scheduled()) {
-           interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+           schedule(interEvent, int_time);
        }
     }
 }
@@ -606,6 +617,8 @@ void
 IGbE::cpuPostInt()
 {
 
+    postedInterrupts++;
+
     if (!(regs.icr() & regs.imr)) {
         DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
         return;
@@ -615,24 +628,24 @@ IGbE::cpuPostInt()
 
 
     if (interEvent.scheduled()) {
-        interEvent.deschedule();
+        deschedule(interEvent);
     }
 
     if (rdtrEvent.scheduled()) {
         regs.icr.rxt0(1);
-        rdtrEvent.deschedule();
+        deschedule(rdtrEvent);
     }
     if (radvEvent.scheduled()) {
         regs.icr.rxt0(1);
-        radvEvent.deschedule();
+        deschedule(radvEvent);
     }
     if (tadvEvent.scheduled()) {
         regs.icr.txdw(1);
-        tadvEvent.deschedule();
+        deschedule(tadvEvent);
     }
     if (tidvEvent.scheduled()) {
         regs.icr.txdw(1);
-        tidvEvent.deschedule();
+        deschedule(tidvEvent);
     }
 
     regs.icr.int_assert(1);
@@ -641,6 +654,7 @@ IGbE::cpuPostInt()
 
     intrPost();
 
+    lastInterrupt = curTick;
 }
 
 void
@@ -663,7 +677,7 @@ IGbE::chkInterrupt()
     if (!(regs.icr() & regs.imr)) {
         DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
         if (interEvent.scheduled())
-           interEvent.deschedule();
+           deschedule(interEvent);
         if (regs.icr.int_assert())
             cpuClearInt();
     }
@@ -677,7 +691,8 @@ IGbE::chkInterrupt()
             if (!interEvent.scheduled()) {
                DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
                        * 256 * regs.itr.interval());
-               interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+               schedule(interEvent,
+                   curTick + Clock::Int::ns * 256 * regs.itr.interval());
             }
         }
     }
@@ -707,7 +722,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet)
     pktPtr = packet;
     pktDone = false;
     igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
-            packet->length, &pktEvent, packet->data);
+            packet->length, &pktEvent, packet->data, igbe->rxWriteDelay);
 }
 
 void
@@ -785,21 +800,21 @@ IGbE::RxDescCache::pktComplete()
     if (igbe->regs.rdtr.delay()) {
         DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
                 igbe->regs.rdtr.delay() * igbe->intClock());
-        igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
-                    igbe->intClock(),true);
+        igbe->reschedule(igbe->rdtrEvent,
+            curTick + igbe->regs.rdtr.delay() * igbe->intClock(), true);
     }
 
-    if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
+    if (igbe->regs.radv.idv()) {
         DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
                 igbe->regs.radv.idv() * igbe->intClock());
         if (!igbe->radvEvent.scheduled()) {
-            igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
-                    igbe->intClock());
+            igbe->schedule(igbe->radvEvent,
+                curTick + igbe->regs.radv.idv() * igbe->intClock());
         }
     }
 
     // if neither radv or rdtr, maybe itr is set...
-    if (!igbe->regs.rdtr.delay()) {
+    if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
         DPRINTF(EthernetSM, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
         igbe->postInterrupt(IT_RXT);
     }
@@ -925,7 +940,7 @@ IGbE::TxDescCache::getPacketData(EthPacketPtr p)
 
     DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length);
     igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
-            TxdOp::getLen(desc), &pktEvent, p->data + p->length);
+            TxdOp::getLen(desc), &pktEvent, p->data + p->length, igbe->txReadDelay);
 
 
 }
@@ -1026,15 +1041,15 @@ IGbE::TxDescCache::pktComplete()
         DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
         if (igbe->regs.tidv.idv()) {
             DPRINTF(EthernetDesc, "setting tidv\n");
-            igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
-                        igbe->intClock(), true);
+            igbe->reschedule(igbe->tidvEvent,
+                curTick + igbe->regs.tidv.idv() * igbe->intClock(), true);
         }
 
         if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
             DPRINTF(EthernetDesc, "setting tadv\n");
             if (!igbe->tadvEvent.scheduled()) {
-                igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
-                        igbe->intClock());
+                igbe->schedule(igbe->tadvEvent,
+                    curTick + igbe->regs.tadv.idv() * igbe->intClock());
             }
         }
     }
@@ -1112,9 +1127,9 @@ IGbE::TxDescCache::hasOutstandingEvents()
 void
 IGbE::restartClock()
 {
-    if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
-            SimObject::Running)
-        tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
+    if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
+        getState() == SimObject::Running)
+        schedule(tickEvent, (curTick / ticks(1)) * ticks(1) + ticks(1));
 }
 
 unsigned int
@@ -1133,7 +1148,7 @@ IGbE::drain(Event *de)
     rxTick = false;
 
     if (tickEvent.scheduled())
-        tickEvent.deschedule();
+        deschedule(tickEvent);
 
     if (count)
         changeState(Draining);
@@ -1393,6 +1408,7 @@ IGbE::txWire()
 
         txBytes += txFifo.front()->length;
         txPackets++;
+        txFifoTick = false;
 
         txFifo.pop();
     } else {
@@ -1417,7 +1433,7 @@ IGbE::tick()
 
 
     if (rxTick || txTick || txFifoTick)
-        tickEvent.schedule(curTick + ticks(1));
+        schedule(tickEvent, curTick + ticks(1));
 }
 
 void
@@ -1446,6 +1462,7 @@ IGbE::serialize(std::ostream &os)
     SERIALIZE_SCALAR(eeDataBits);
     SERIALIZE_SCALAR(eeOpcode);
     SERIALIZE_SCALAR(eeAddr);
+    SERIALIZE_SCALAR(lastInterrupt);
     SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
 
     rxFifo.serialize("rxfifo", os);
@@ -1497,6 +1514,7 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(eeDataBits);
     UNSERIALIZE_SCALAR(eeOpcode);
     UNSERIALIZE_SCALAR(eeAddr);
+    UNSERIALIZE_SCALAR(lastInterrupt);
     UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
 
     rxFifo.unserialize("rxfifo", cp, section);
@@ -1521,19 +1539,19 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(inter_time);
 
     if (rdtr_time)
-        rdtrEvent.schedule(rdtr_time);
+        schedule(rdtrEvent, rdtr_time);
 
     if (radv_time)
-        radvEvent.schedule(radv_time);
+        schedule(radvEvent, radv_time);
 
     if (tidv_time)
-        tidvEvent.schedule(tidv_time);
+        schedule(tidvEvent, tidv_time);
 
     if (tadv_time)
-        tadvEvent.schedule(tadv_time);
+        schedule(tadvEvent, tadv_time);
 
     if (inter_time)
-        interEvent.schedule(inter_time);
+        schedule(interEvent, inter_time);
 
     txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section));